2006

W.-S. Wang and M. Orshansky, "Robust estimation of parametric yield under limited descriptions of uncertainty," in Proc. of International Conference on Computer Aided Design, pp. 884-890, San Jose, CA, 2006. [PDF]

W.-S. Wang, M. Orshansky, "Robust Timing Analysis under Uncertainty for Timing Sign-Off," in Proc. of Design Automation Conference, pp. 161-166, July 2006.

A. Singh, M. Mani, R. Puri and M. Orshansky, "Gain-Based Technology Mapping for Minimum Runtime Leakage under Input Vector Uncertainty," in Proc. of Design Automation Conference, pp. 522-527, July 2006. [PDF]

M. Mani, A. Singh, and M. Orshansky, "Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization," to appear in International Conference on Computer Aided Design, 2006. Best Paper Award [PDF]

B. Zhang, A. Arapostathis, S. Nassif, and M. Orshansky, "Analytical Modeling of SRAM Dynamic Stability," to appear in International Conference on Computer Aided Design, 2006. [PDF]

A. Ramalingam, A. K. Singh, S. Nassif, G.-J. Nam, D. Pan, and M. Orshansky, "An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis," to appear in International Conference on Computer Aided Design, 2006. [PDF]

A. Ramalingam, A. K. Singh, S. Nassif, G.-J. Nam, D. Pan, and M. Orshansky, "An Accurate Sparse Matrix Based Framework for Statistical Static Timing Analysis," Proc. of Austin Conference on Systems and Circuits, Austin, Texas, 2006. [PDF]

M. Orshansky, "Statistical Minimization of Total Power under Timing Yield Constraints," in Proc. of International Conference on IC Design and Technology, Padua, Italy, 2006. Invited.

W.-S. Wang and M. Orshansky, "Robust Estimation of Parametric Yield under Limited Variational Data," to appear in International Conference on Computer Aided Design, 2006.

M. Mani, M. Sharma, Y. Zhan and M. Orshansky, "Application of Statistical Sizing using SOCP in an Industrial Design Flow," Austin Conference on Systems and Circuits, Austin, Texas, 2006. [PDF]

B. Zhang, A. Arapostathis, S. Nassif, and M. Orshansky, "Analytical Prediction of Transient Error Susceptibility of SRAM Cells," Austin Conference on Systems and Circuits, Austin, Texas, 2006

M. Mani, M. Sharma, M. Orshansky, "Application of a Fast Statistical Sizing Algorithm based on Second Order Conic Programming in the Industrial Microprocessor Design Flow," Proc. of Great Lake Symposium on VLSI, pp. 372-375, Philadelphia, PN, 2006. [PDF]

B. Zhang, W. Wang, and M. Orshansky, "Static Analysis of Circuit Soft-Error Susceptibility for Cell-Based Design," Proc. of International Symposium on Quality Electronic Design (ISQED), San Jose, CA, 2006. Best Paper Award.

2005

B. Zhang and M. Orshansky, "SER Prediction by Symbolic Simulation of the Propagation and Filtering of Transient Faulty Pulses," Workshop on System Effects of Logic Soft Errors, Urbana-Champaign, IL, 2005

A. Singh, M. Mani, and M. Orshansky, "Statistical Technology Mapping for Parametric Yield," Proc. of International Conference on Computer-Aided Design, pp. 511-518, San Jose, CA, 2005 [PDF]

J. Kim and M. Orshansky "Towards A Formal Hierarchical Framework for Probabilistic Power-Performance Optimization", SRC Techcon, Portland, Oregon, 2005

M. Mani, A. Devgan, and M. Orshansky, "An Efficient Algorithm for Statistical Minimization of Total Power under Timing Yield Constraints", Proc. of Design Automation Conference, 2005 Best Paper Award [PDF]

B. Zhang, W.-S. Wang, M. Orshansky, "FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs," to appear in the ISQED 06. [PDF]

B. Zhang, W.-S. Wang, M. Orshansky, "Symbolic Simulation of the Propagation and Filtering of Transient Faulty Pulses," Workshop on System Effects of Logic Soft Errors, April 2005. [PDF] [SLIDES]

2004

M. Mani and M. Orshansky, "A new statistical optimization algorithm for gate sizing," Proc. of International Conference on Computer Design, 2004.

M. Liu, W.-S. Wang, M. Orshansky, "Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation," International Symposium on Low Power Electronics and Design, pp. 2-7, August 2004. [PDF]

D. G. Chinnery, B. Thompson, M. Orshansky, K. Keutzer "Power Minimization with Multiple Supply Voltages and Multiple Threshold Voltages," 2004. [PDF]

M. Orshansky, A. Bandyopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations," Design Automation Conference, pp. 337-342, June 2004. [PDF]

2003

D. Nguyen, A. Davare, M. Orshansky, D. Chinnery, B. Thompson, K. Keutzer, "Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization [logic IC design]," International Symposium on Low Power Electronics and Design, pp. 158-163, August 2003. [PDF]

2002

M. Orshansky, K. Keutzer, "From Blind Certainty to Informed Uncertainty," TAU Workshop, December 2002. [PDF]

M. Orshansky, K. Keutzer, "A general probabilistic framework for worst case timing analysis," Design Automation Conference, pp. 556-561, June 2002. [PDF]

M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 544-553, May 2002. [PDF]

2001

M. Orshansky, J. An, C. Jiang, B. Liu, C. Ricoobene, C. Hu, "Efficient generation of pre-silicon MOS model parameters for early circuit design," IEEE Journal of Solid-State Circuits, pp. 156-159, January 2001. [PDF]

2000

M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, "Impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits," International Conference on Computer Aided Design, pp. 62-67, November 2000. [PDF]

Y. Cao, T. Sato, M. Orshansky, D. Sylvester, C. Hu, "New paradigm of predictive MOSFET and interconnect modeling for early circuit simulation," Custom Integrated Circuits Conference, pp. 201-204, May 2000. [PDF]

1999

M. Orshansky, L. Milor, L. Nguyen, G. Hill, Y. Peng, C. Hu, "Intra-field gate CD variability and its impact on circuit performance," Electron Devices Meeting, pp. 479-482, December 1999. [PDF]

M. Orshansky, J. Chen, C. Hu, "Direct sampling methodology for statistical analysis of scaled CMOS technologies," IEEE Transactions on Semiconductor Manufacturing, pp. 403-408, November 1999. [PDF]

M. Orshansky, C. Spanos, C. Hu, "Circuit performance variability decomposition," International Workshop on Statistical Metrology, pp. 10-13, June 1999. [PDF]

1998

M. Orshansky, J. Chen, C. Hu, "A statistical performance simulation methodology for VLSI circuits," Design Automation Conference, pp. 402-407, June 1998. [PDF]

J. Chen, M. Orshansky, C. Hu, C.-P Wan, "Statistical circuit characterization for deep-submicron CMOS designs," Solid-State Circuits Conferences, pp. 18-19, June 1998. [PDF]

M. Orshansky, D. Sinitsky, P. Scrobohaci, J. Bokor, C. Hu, "Impact of Velocity Overshoot, Polysilicon Depletion, and Inversion Layer Quantization on NMOSFET Scaling," Device Research Conference Digest, pp. 18-19, June 1998. [PDF]

1997

D. Sinitsky, F. Assaderaghi, M. Orshansky, J. Bokor, C. Hu, "Velocity Overshoot Of Electrons and Holes in Si Inversion Layers," Solid-State Electronics, vol. 41, no. 8, August 1997. [PDF]