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Structured digital circuit design has long been left to custom designers because of the significant performance and power improvements between manual and automated results. In recent years, increased cost pressures have pushed industry to develop CAD tools that address this area. Significant progress has been made in the area of random logic placement however little work has been in the area of structured placement. This benchmark suite is a sample of structured industrial circuits comparing a manual solution to automated placement solutions for only the structured portion of the design. Current industrial trends are moving to a mixed flow design where both random logic and structured logic are intermingled creating significant complexity and suboptimality from current placement tools.
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The first benchmark set spba, derives from the manual placement of an actual high-speed microprocessor rotator (barrel shifter) function. Rotate circuits, also known as cyclic shifters, are a simple and common bit operation generally found throughout microprocessor designs, cryptography, imaging, and biometrics. Traditionally, rotators are custom designed because of their highly regular structure and significant routing complexity though some work to automated placement has been explored. Details are described in [1].
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| ‡ | This benchmark contains cell heights larger than the default height. Dragon is not compatible with nondefault heights so large cells were reduced in size for dragon only. The total number of cells modified is 128, a small percentage with little impact on the overall design results. |
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The second benchmark set spba is a standard AND/OR logic tree common throughout datapath design mimicing the structure of comparators. Two signals, a_o and sd[j], are driven into an AND gate with the data inputs and then into an OR tree. The output of the OR tree is then ORed with a set signal ei, and the result is latched. This structure is used in many applications, such as translation buffers and structured content addressable-memory circuits. Details are described in [1].
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References
| [1] | Samuel I. Ward, et. al. “Quantifying Academic Placer Performance on Custom Designs' ISPD 2011, pp.. |
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