IEEE/ACM Workshop on Variability Modeling and Characterization

(VMC) 2012

November 8th,  2012

Hilton San Jose, CA

Registration through ICCAD

(Programs of previous workshops are available: 2011, 2010, 2009, 2008)

Call for Abstract: submission due on Sept. 14, 2012; accepted abstract will be presented at the poster session

It is widely recognized that process variation is emerging as a fundamental challenge to IC design in scaled CMOS technology; and it will have profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled with improvements in the manufacturing process, the industry is starting to accept the fact that some of the effects are better mitigated during the design process. Handling variability in the design process will require accurate and appropriate models of variability and its dependence on designable parameters (i.e. layout), and its spatial and temporal distributions. It also requires carefully designed test structures and proper statistical data analysis methods to extract meaningful models from large volumes of silicon measurements. The resulting compact modeling of systematic, random, spatial, and temporal variations is essential to abstract the physical level variations into a format the designers (and more importantly, the tools they use) can utilize. This workshop provides a forum to discuss current practice as well as near future research needs in test structure design, variability characterization, compact variability modeling, and statistical simulation.

Key Topics

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Physics mechanisms and technology trends of device-level variations

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   First-principles simulation methods for predicting variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Time-dependent variation and their interaction with other variation sources

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Compact modeling of variations in devices and interconnect

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Device and circuit level modeling techniques

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Test structure design for variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Variability characterization, bounding and extraction

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Statistical data analysis and model extraction methods

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Novel implementation and simulation techniques for dealing with variability

Tentative Agenda

8:50 9:00am     Opening Remarks

Session 1: Emerging memory technology

9:00 9:30am     Keynote: Philip Wong (Stanford University)

Variability in Emerging Memory Devices: Physical Understanding, Modeling, and Mitigation

9:30 10:00am Kaushik Roy (Purdue University)

Spin Transfer Torque Memories: Device, Circuit, & Architecture Considerations

10:00 10:30am Morning Break/Discussion

Session 2: Variability in SRAM

10:30 11:00am Asen Asenov (University of Glasgow)

Simulation Based Device-SRAM Co-design in Advanced CMOS Technology Generations

11:00 11:30am David Burnett (GLOBALFOUNDRIES)

Practical Approaches to Margining for SRAM Variation

11:30 12:00pm Ken Takeuchi (Chuo University)

Variability and Failure Recovery of SRAM and Flash Memory

12:00 1:10pm Lunch

Session 3: Near-threshold design

1:10 1:40pm Keynote: Vivek De (Intel)

Near Threshold Voltage (NTV) Design in Nanoscale CMOS

1:40 2:10pm Makoto Takamiya (University of Tokyo)

Extremely Low Power VLSI Circuits with Low Voltage Operation

2:10 2:40pm Ronald Dreslinski (University of Michigan)

Techniques for Addressing Variation in Near-Threshold Wide-SIMD Architectures

2:40 3:10pm Afternoon Break/Discussion

3:10 4:00pm Poster Presentation

4:00 5:00pm Poster Session

Technical Program Committee

Co-chairs: Hidetoshi Onodera, Kyoto University, onodera AT vlsi DOT kuee DOT kyoto-u DOT ac DOT jp

Yu (Kevin) Cao, Arizona State University, ycao AT asu DOT edu

 

Asen Asenov, University of Glasgow

Chris Kim, University of Minnesota

Colin McAndrew, Freescale Semiconductor

Vijay Reddy, Texas Instruments

Takashi Sato, Kyoto University

 

Sponsors:

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\ieee.jpg          Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\edsjpeg.jpg     Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\acm.jpg   Description: Description: Description: Description: Description: Description: Description: SRC_GRC_logo_c.jpg            

Last updated on September 25, 2012. Contents subject to change. All rights reserved.