IEEE/ACM Workshop on Variability Modeling and Characterization

(VMC) 2013

November 21st,  2013

Hilton San Jose, CA

Registration through ICCAD

(Programs of previous workshops are available: 2012, 2011, 2010, 2009, 2008)

Call for Abstract: submission due on Sept. 30, 2013; accepted abstract will be presented at the poster session

It is widely recognized that process variation is emerging as a fundamental challenge to IC design in scaled CMOS technology; and it will have profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled with improvements in the manufacturing process, the industry is starting to accept the fact that some of the effects are better mitigated during the design process. Handling variability in the design process will require accurate and appropriate models of variability and its dependence on designable parameters (i.e. layout), and its spatial and temporal distributions. It also requires carefully designed test structures and proper statistical data analysis methods to extract meaningful models from large volumes of silicon measurements. The resulting compact modeling of systematic, random, spatial, and temporal variations is essential to abstract the physical level variations into a format the designers (and more importantly, the tools they use) can utilize. This workshop provides a forum to discuss current practice as well as near future research needs in test structure design, variability characterization, compact variability modeling, and statistical simulation.

Key Topics

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Physics mechanisms and technology trends of device-level variations

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   First-principles simulation methods for predicting variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Time-dependent variation and their interaction with other variation sources

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Compact modeling of variations in devices and interconnect

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Device and circuit level modeling techniques

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Test structure design for variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Design interface with manufacturing and solutions for variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Variability characterization, bounding and extraction

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Statistical data analysis and model extraction methods

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Novel implementation and simulation techniques for dealing with variability

Tentative Agenda

8:50 9:00am     Opening Remarks

Session 1: Litho-Design Interface

9:00 9:30am     Keynote: Lars Liebmann (IBM Corporation)

Novel Patterning-Design Interfaces to Manage Variability in Advanced Technology Nodes

9:30 10:00am J. Andres Torres (Mentor Graphics)

Variability in Directed Self Assembly

10:00 10:30am Morning Break/Discussion

Session 2: Reliability Modeling

10:30 11:00am Steve Ramey (Intel)

On FinFET reliability

11:00 11:30am Ahmed Ramadan (Mentor Graphics)

on "simulator interface for reliability modeling"

11:30 12:00pm Mitiko Miura-Mattausch (Hiroshima U.)

Modeling of Advanced CMOS Degradation for Reliable Circuit Design

12:00 1:10pm Lunch

Session 3: On-chip sensors and Test Structures

1:10 1:40pm Keith A. Jenkins (IBM)

On-chip Measurements for Device Variability (tentative)

1:40 2:10pm Takakshi Sato (Kyoto Univ.)

A Device Array for Flexible BTI Characterization

2:10 2:40pm Tanya Nigam (GLOBALFOUNDRIES)

TBD

2:40 3:10pm Afternoon Break/Discussion

3:10 4:00pm Poster Presentations (3 minutes overview for each poster)

4:00 5:00pm Poster Session

Technical Program Committee

Co-chairs: Hidetoshi Onodera, Kyoto University, onodera AT vlsi DOT kuee DOT kyoto-u DOT ac DOT jp

David Z. Pan, University of Texas at Austin, dpan AT mail DOT utexas DOT edu

Rasit O Topaloglu, IBM, rasit AT us DOT ibm DOT com

 

Asen Asenov, University of Glasgow

Yu (Kevin) Cao, Arizona State University

Chris Kim, University of Minnesota

Frank Liu, IBM Austin Research Lab

Colin McAndrew, Freescale Semiconductor

Vijay Reddy, Texas Instruments

Takashi Sato, Kyoto University

 

Sponsors:

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\ieee.jpg          Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\edsjpeg.jpg     Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\acm.jpg   Description: Description: Description: Description: Description: Description: Description: SRC_GRC_logo_c.jpg            

Last updated on September 22, 2013. Contents subject to change. All rights reserved.