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Current Research Topics

I am currently looking into two interesting aspects of tools for nano-CMOS circuit design: performance and design productivity enhancement.

Modeling and Performance Optimization of Strained Silicon Devices: S/D (source/drain) type SiGe transistors have peculiar property that the mobility of channel can be increased by modulating diffusion area.  I am looking into modeling this effect at standard cell granularity.  This would directly lead to layout optimization (for performance) of standard cell libraries if they are to be fabricated using S/D SiGe transistors.

Physical Design for Structured ASICs: Tight turn-around-time and low yield ramp-up rates mandate use of some sort of structured (regular) layout for increasing design productivity and easier design flow (simpler extraction, signal itegrity, yield model).  Structured ASICs are one great choice in this context.  I have developed  algorithms for high-quality placement algorithm for structured ASICs which can exploit existing standard-cell type commercial tools.

Previous Research Topics

In the past I have worked on following topics:

Dynamic Control of Clock Skew Originating from non-uniform Thermal Profiles I (along with my collegues at Politecnico di Torino, Italy) researched various techniques for estimating and correcting the clock skew at runtime for a chip which over its period of operation goes through various temperature profiles. Broadly, we proposed and inserted minimum number of variable delay clock buffer with a small controller. The controller decides the runtime configuration of the variable delay buffers using a few (4-5) on-chip temperature sensors.

Mitigating Impact of NBTI in Gated Clock Trees: Clock tree are major power hog and very often are gated for power reduction. This unique combination of high power (leading to high temperature) and non-uniform switching activity (due to gating) causes serious NBTI reliability problem in clock buffers. I am researching ways to estimate and contain the detrimental NBTI impact to increase lifetime of the device.

Regularity Driven Synthesis It is widely accepted that due to printability and yield concerns, the layout of future devices will need to conform to strictly regular patterns. In this project I researched and evaluated techniques to capture the structural regularity (similarity) at the RTL level. Smart logic synthesis techniques are then applied to transform the design into standard cells while still preserving the modularity of the design.

Congestion and Porosity Aware Buffer Insertion During Placement In this project I (along with my colleague Donnie) researched ways to improve the whitespace allocation and buffer insertion so as not to hurt the routability of the design (notice that buffering along net reduces the freedom available to router to route it) and to promote faster design closure by preventing the rippling effect of layout changes.

Publications [Journals/Conferences/Thesis]

Journals

  1. “A MOS Approach to CMOS DET Flop-Flop Design”: P. Varma, B.S. Panwar, Ashutosh Chakraborty, Dheeraj Kapoor TCAS 2002, Vol 49, No.7. pp 1-4
  2. “Implementation of a Thermal Management Unit for Canceling Temperature-Dependent Skew Variations”: Ashutosh Chakraborty, et al.: Integr. VLSI Journal 2008, Vol 41, No. 1, pp. 2-8.
  3. “Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers”: Ashutosh Chakraborty, et al.: TVLSI 2008, Vol 16, No. 6, pp. 639-649.
  4. “ECO Placement for Stress Aware Timing Optimization for Si-Ge Devices”: Ashutosh Chakraborty and David Z. Pan (under preparation)

Conferences

  1. “Low-Voltage, Double-Edge-Triggered Flip Flop”: Pradeep Varma, Ashutosh Chakraborty, PATMOS 2003. pp 11-21
  2. “Evaluating Regularity Extraction in Logic Synthesis”: Ashutosh Chakraborty, Davide Pandini, A. Macii, E. Macii, M. Poncino, ISSCS 2005, pp. 641-644
  3. “Exploiting Cross-Channel Correlation for Energy Efficient LCD Bus Encoding”: Ashutosh Chakraborty, Enrico Macii, Massimo Poncino, PATMOS 2005. pp 297-307
  4. “Energy-Efficient Encoding for HDCP Protected Digital LCD Interfaces”: Ashutosh Chakraborty, Enrico Macii, Massimo Poncino, ISSCS 2005. pp 19-22
  5. “Dynamic Management of Thermally-Induced Clock Skew”: Ashutosh Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, M. Poncino, PATMOS 2006. pp 214-224
  6. “Implications of Ultra Low Voltage Devices on Techniques and Tools for High-Performance VLSI Circuits”: Ashutosh Chakraborty, K. Duraisami, A. Macii, E. Macii, M. Poncino, A. Sathanur, P. Sithambaram, ISCAS
    2006 (invited), pp 4-7
  7. “Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers”: Ashutosh Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, et al. ISLPED 2006, pp 162-167
  8. “Thermal Resilient Bounded-Skew Clock Tree Optimization Methodology”: Ashutosh Chakraborty, P. Sithambaram, K. Duraisami, A. Macii, E. Macii, M. Poncino, DATE 2006. pp 832-837
  9. “Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon”: Ashutosh Chakraborty, Sean X. Shi, David Pan: DATE 2008, pp 849-855
  10. “An Integrated Nonlinear Placement Framework with Congestion and Porosity Aware Buffer Planning”: Tung-Chieh Chen, Ashutosh Chakraborty, David Z. Pan: DAC 2008, pp 702-707
  11. “Analysis and Optimization of NBTI Induced Clock Skew in Gated Clock Trees”: Ashutosh Chakraborty, Gokul Ganesan and David Z. Pan: DATE 2009(to appear)
  12. "On Stress Aware Active Area Sizing, Gate Sizing, and Repeater Insertion”: Ashutosh Chakraborty and David Z. Pan: ISPD 2009 (to appear)
  13. “RegPlace: A High Quality Opensource Placement Framework for Structured ASICs”: Ashutosh Chakraborty, Anurag Kumar and David Z. Pan: (submitted)

Thesis

  1. “A MOS Approach to CMOS Double-Edge-Triggered Flip-Flop Design”: Ashutosh Chakraborty: Undergraduate Thesis, Department of Electrical Engineering, IIT Delhi, 2002
  2. “Analysis and Control of Clock Gating Aggravated NBTI Induced Clock Skew”: Ashutosh Chakraborty, Masters Report, University of Texas at Austin, 2008