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Current Research Topics

I am currently looking into two interesting problems.

Modeling and Performance Optimization of Strained Silicon Devices: S/D (source/drain) type SiGe transistors have peculiar property that the mobility of channel can be increased by modulating diffusion area.  I am looking into modeling this effect at standard cell granularity.  This would directly lead to layout optimization (for performance) of standard cell libraries if they are to be fabricated using S/D SiGe transistors. (relevant publication)

Mitigating Impact of NBTI in Gated Clock Trees: Clock tree are major power hog and very often are gated. This unique combination of high power (leading to high temperature) and non-uniform switching activity (due to gating) causes very serious (NBTI relateD) reliability problem in clock buffers. I am researching ways to estimate and contain the detrimental NBTI impact for increasing usable lifetime of the device.

Previous Research Topics

In the past I have worked on following topics:

Dynamic Control of Clock Skew Originating from non-uniform Thermal Profiles I (along with my collegues at Politecnico di Torino, Italy) researched various techniques for estimating and correcting the clock skew at runtime for a chip which over its period of operation goes through various temperature profiles. Broadly, we proposed and inserted minimum number of variable delay clock buffer with a small controller. The controller decides the runtime configuration of the variable delay buffers using a few (4-5) on-chip temperature sensors.

Regularity Driven Synthesis It is widely accepted that due to printability and yield concerns, the layout of future devices will need to conform to strictly regular patterns. In this project I researched and evaluated techniques to capture the structural regularity (similarity) at the RTL level. Smart logic synthesis techniques are then applied to transform the design into standard cells while still preserving the modularity of the design.

Congestion and Porosity Aware Buffer Insertion During Placement In this project I (along with my colleague Donnie) researched ways to improve the whitespace allocation and buffer insertion so as not to hurt the routability of the design (notice that buffering along net reduces the freedom available to router to route it) and to promote faster design closure by preventing the rippling effect of layout changes.

Publications

Journals

  1. Ashutosh Chakraborty, K Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, M. Poncino, “Design and Deployment of Tunable Delay Buffers to Mitigate Thermal Profile Induced Dynamic Clock Skew Violations", TVLSI (to appear) view
  2. P. Varma, B. S. Varma, Ashutosh Chakraborty, D. Kapoor, "A MOS Approach to CMOS DET flip-flop design", IEEE Transactions on Circuits and Systems TCAS 2002 (view)

Conferences

  1. Tung-Chieh Chen, Ashutosh Chakraborty, David Pan, "An Integrated Nonlinear Placement Framework with Congestion and Porosity Aware Buffer Planning", DAC 2008 (view pdf)
  2. Ashutosh Chakraborty, Sean X. Shi, David Pan, "Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices", DATE 2008 (view pdf)
  3. Ashutosh Chakraborty, D. Duraisami, P. Sithambaram, A. Macii, E. Macii, M. Poncino, "Thermal Resilient Bounded-skew Clock Tree Optimization Methodology", DATE 2006 (view pdf)
  4. Ashutosh Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, L. Benini, A. Macii, E. Macii, M. Poncino, "Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers", ISLPED 2006 (view pdf)
  5. Ashutosh Chakraborty, K. Duraisami, A. Macii, E. Macii, M. Poncino, A. Sathanur, P. Sithambaram, "Implications of Ultra Low-Voltage Device on Design Techniques controlling Leakage in NanoCMOS Circuits", ISCAS 2006 (invited paper) (view pdf)
  6. Ashutosh Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, A. Macii, E. Macii, M. Poncino", PATMOS 2006 (view pdf)
  7. Ashutosh Chakraborty, Enrico Macii, Massimo Poncino, "Energy-Efficient Encoding for HDCP Protected Digital LCD Interfaces", ISSCS 2005 (view pdf)
  8. Ashutosh Chakraborty, Enrico Macii, Massimo Poncino, "Exploiting Cross-Channel Correlation for Energy Efficient LCD Bus Encoding", PATMOS 2005 (view pdf)
  9. Ashutosh Chakraborty, Davide Pandini, A. Macii. E. Macii, M. Poncino, "Evaluating Regularity Extraction in Logic Synthesis", ISSCS 2005 (view pdf)
  10. Pradeep Varma, Ashutosh Chakraborty, "Low-Voltage Double-Edge-Triggered Flip Flop", PATMOS 2003 (view pdf)