TUNES-P
Texas UNcertainty EStimator for Permanent Uncertainty

Introduction
Welcome to TUNES-P. TUNES-P is a design space exploration system developed at the University of Texas and University of Michigan to enable a comprehensive analysis of design choices facing the system designer with the special focus on transient reliability and parametric yield. TUNES-P is the first tool that has reliability and variability as central objectives. Reliability and variability-centric design space exploration requires analysis across-the-hierarchy since it is clear that the optimum set of solutions depends on technology, circuits, and architectural solutions. At the time of its final release TUNES-P will encompass models enabling analysis of several design hierarchy layers, and also include the modeling of different circuit fabrics, methods of reliability-hardening, and communication paradigms.

TUNES-P is a fully analytical engine. It is built upon the growing body of work in probabilistic design modeling and analysis. Most of the models used in the tool have been developed by the creators of the TUNES-P.
TUNES-P Flow
References

[1] ITRS (International Technology Roadmap for Semiconductors) 2003 Edition
[2] M. Orshansky, A. Bandyopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations," Design Automation Conference, pp. 337-342, June 2004.
[3] M. Orshansky, L. Milor, P. Chen, K. Keutzer, C. Hu, "Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 544-553, May 2002.
[4] R. Rao, A. Devgan, D. Blaauw, and D. Sylvester, "Parametric yield estimation considering leakage variability", Design Automation Conference, pp. 442-447, 2004.
[5] M. Liu, W. S. Wang, M. Orshansky, "Leakage power reduction by dual-Vth designs under probabilistic analysis of Vth variation," International Symposium on Low Power Electronics and Design , pp. 2-7, August 2004.
[6] A. Agarwal, V. Zolotov, and D. Blaauw, "Statisitcal Clock Skew Analysis Considering Intradie-Process Variations," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol. 23, No. 8, pp. 1231-1242, August 2004.
[7] M. Hashimoto, T. Yamamoto, and H. Onodera, "Statistical Analysis of Clock Skew Variation in H-tree Structure," Proceedings of the Sixth International Symposium on Quality Electronic Design, pp. 402-407, March 2005.

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