Zhang, Bin
I received my BS degree from Shanghai Jiao Tong University, MS from Peking University, and PhD from University of Texas at Austin, USA. I did my PhD research under the supervision of Prof. Michael Orshansky in the Robust IC Desgin Lab of Department of Electrical and Computer Engineering, University of Texas at Austin. I also worked at Cisco Sytems and Intrinsity Inc. I received the Best Paper Award from International Sysmposium of Quality Electronics Design (ISQED), for my work in soft error analysis.
Research Areas
- IC reliability modeling and analysis
- soft error analysis
- permanent error (NBTI, TDDB etc.) modeling and analysis
- Robust IC design
- Low power IC design
Awards
- IBM Research Award, B. Zhang, Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation, in Graduate And Industry Networking Conference, University of Texas at Austin, 2008.
- Best Paper Award, B. Zhang, W.-S. Wang and M. Orshansky, FASER: Fast analysis of soft error susceptibility for cell-based designs, in International Symposium on Quality Electronic Design, San Jose, CA, 2006.
Curriculum Vitae
Publications
- A. Ramalingam, B. Zhang, A. Devgan, D. Z. Pan, Sleep transistor sizing using timing criticality and temporal currents, in Proc. Asia and South Pacific Design Automation Conference, 2005, pp. 1094-1097, Shanghai, China.
- B. Zhang, W.-S. Wang and M. Orshansky, FASER: Fast analysis of soft error susceptibility for cell-based designs, in Proc. International Symposium on Quality Electronic Design, 2006, pp. 755-760, San Jose, CA. (Best Paper Award)
- K. Constantinides, S. Plaza, J. Blome, B. Zhang, V. Bertacco, S. Mahlke, T. Austin and M. Orshansky, BulletProof: a defect-tolerant CMP switch architecture, in Proc. International Symposium on High-Performance Computer Architecture, 2006, pp. 5-16, Austin, TX.
- B. Zhang, A. Arapostathis, S. Nassif and M. Orshansky, Analytical modeling of SRAM dynamic stability, in Proc. International Conference on Computer Aided Design, 2006, pp. 315-322, San Jose, CA.
- K. Constantinides, S. Plaza, J. Blome, V. Bertacco, S. Mahlke, T. Austin, B. Zhang, and M. Orshansky, Architecting a reliable CMP switch architecture, in ACM Transations on Architecture and Code Optimization, Vol. 4, No. 1, March 2007.
- B. Zhang and M. Orshansky, Modeling of NBTI-Induced PMOS Degradation under Arbitrary Dynamic Temperature Variation, in Proc. International Symposium on Quality Electronic Design, 2008, pp. 774-779, San Jose, CA.
- B. Zhang and M. Orshansky, Online Circuit Reliability Monitoring, in Proc. Great Lake Symposium on VLSI, 2009, Boston, MA.
Contact Information