DUO    DING                           DING at CERC dot UTEXAS dot EDU

EDUCATION

08/2008-present                                      PhD Program in ECE Dept., graduation expected 2011

Computer Engineering Research Center - UT Austin Design Automation Group

Major GPA        3.89 / 4.0

08/2006-06/2008                                     MSE in Electronic and Computer Engineering Dept. June 2008

                                                                              University of Texas at Austin, Austin, TX

08/2002-06/2006                                     B.S in Electronic and Computer Engineering Dept. June 2006

                                                                              Harbin Institute of Technology, Harbin, CHINA

AREA OF INTEREST AND CONCENTRATION

                                                                Novel Applications for Design for Manufacturability/Yield

                                        EDA/CAD for VLSI Physical Design Automation

                                                                CAD for Emerging Technologies (3D IC, Nano-technology, GPU/Network-on-Chip)

GRADUATE LEVEL COURSES AT UT AUSTIN

Physical Design for VLSI CAD              CMOS Digital IC Design        Data Mining           Stochastic Processes       Applied Optimizations

Digital Signal Processing                         VLSI Simulation Methods      VLSI CAD Optimization            VLSI-I       Optical Interconnect

GRADUATE RESEARCH EXPERIENCE

Fall07-Present         Graduate Research: UT Austin Design Automation Group                                       

♦ Design for Manufacturability/Yield - process hotspot detection for sub-65nm technology

♦ Physical design CAD (partitioning/placement/routing) for on-chip nano-technology

♦ CAD for power/energy aware mapping/scheduling for multi/many core-on-chip designs

♦ Fast SRAM yield simulation under lithography process variations     

GRADUATE ACADEMIC EXPERIENCE

Fall08                     Term Project for "Physical Design for VLSI CAD"

                                                ♦ A low power optical routing framework for on-chip nano-photonic integration

                                                ♦ i.e ISPD08 benchmarks, C/C++ implementation, Integer Linear Programming, GLPK solver

Spr08                      Term Project for "Advanced Topics for Data Mining"

                                                ♦ A machine learning (ANN) based fast lithographic hotspot detection framework

                                                ♦ i.e Artificial Neural Network(MATLAB), TCL/TK C/C++ coding, CALIBRE simulation.

Fall07                     Term Project for "VLSI CAD Optimization"                                                                                   

                                                ♦ Energy Aware CAD Flow for Voltage-Frequency Island based Network-on-Chips.

                                                ♦ i.e energy aware task mapping/scheduling algorithms implemented in C/C++

Fall07                     Term Project for "VLSI Simulation"                                                                                         

                                                ♦ Novel Fast SRAM Yield Simulation under random doping induced threshold variations.

                                                ♦ i.e fast Monte Carlo / modified mixture importance sampling; C/C++, TCL, HSPICE and MATLAB

Spr07                      Term Project for "VLSI-I"                                                                                                                    

                                                ♦ A 0.18 micron 18mw 4MHz Fix-Point 64/128 FFT Kernel for IEEE 802.11 wireless protocol

                                                ♦ i.e Cadence / Synopsys tools and Verilog HDL

MAJOR CODING PROJECTS

                                                ♦ A 0.18um 128 point 18mw 4MHz FFT Kernel in Verilog HDL

                                                ♦ Fast SRAM yield simulation under random doping effects in C/C++

                                                ♦ Spice-like VLSI circuit simulator in C/C++

                                                ♦ Energy aware mapping and task scheduling algorithms for GALS NoC/SoC in C/C++

                                                ♦ Fast lithographic hotspot detection in CALIBRE / TCL / C / MATLAB

                                                ♦ VLSI CAD physical synthesis for on-chip nano-photonic integration in C/C++

PAPER / PUBLICATION

♦Duo Ding and David Z. Pan, "OIL: A Nanophotonic Optical Interconnect Library for a New Photonic Networks-on-Chip Architecture",
International Workshop on System Level Interconnect Prediction (SLIP), California, July 2009

♦ Duo Ding, Yilin Zhang, Haiyu Huang, Ray T. Chen and David Z. Pan, "O-Router: An Optical Routing Framework for Low Power On-Chip Silicon Nano-Photonic Integration",
Design Automation Conference (DAC) 2009

♦Duo Ding, Xiang Wu, Joydeep Ghosh, and David Z. Pan, "Machine Learning based Lithographic Hotspot Detection with Critical Feature Extraction and Classification",
International Conference on IC Design and Technology (ICICDT), Austin, 2009 (awarded as the only Best Student Paper Award)

♦ Wooyoung Jang, Duo Ding and David Z. Pan, “A Voltage-Frequency Island Aware Energy Optimization Framework for Networks-on-Chip”,
Int'l Conference on Computer-Aided Design (ICCAD) 2008

♦Duo Ding and David Z. Pan, "MISR - Mixture Importance Sampling Recipe Optimizations for Fast SRAM Yield Simulation under Fabrication Process Variations",
MSE thesis at ECE Dept. of Univ. of Texas at Austin, May 2008

INTERNSHIP / CO-OP EXPERIENCE

Summer 09            Litho-friendly DFM Internship at Mentor Graphics. Portland, OR

                                ♦ Prototyping novel applications for lithography friendly DFM techniques for fast and accurate hotspot detection, with C/C++ and CALIBRE-API

Summer 08            Summer Research Assistant – UT Austin Design Automation Group, Austin, TX

                                ♦ On-chip nano-photonic simulation/integration for next generation chip multi-processors, with C/C++, TCL/TK

Summer 07            EDA Quality Assurance Internship at Lightspeed^® Inc. Austin, TX                                                                         

                                ♦ QA and testing for Lightspeed^® commercial EDA product with TCL/TK, C/C++coding under Fedora7 Linux

SKILLS          

Calibre, Cadence, Hspice/Spectre; C/C++, TCL/TK, MATLAB, Verilog HDL; Linux/Unix, Windows, DOS