Part B - ALU
Arithmetic Logic Unit
Index
The goal of Lab2B remains the same as that of Lab2A--to implement a fully functional circuit using a VLSI design flow. This assignment adds one step to the design process that you have not completed yet. You need to incorporate your adder to create and expand a higher-level chip. The two factors that determine the success of your circuit also remain the same. This circuit will be built and tested for functionality and speed.
In this assignment, you will incorporate your adder in the design of a full Arithmetic and Logic Unit (alu) of a 16-bit RISC microprocessor. To do this, you will need to follow similar steps as those you took in Lab 2A. First, you must choose a design based on the specification of the alu given below. After choosing a design, you will create your circuit in the Cadence schematic program. You will use Verilog-XL to test the functionality of the new circuit using an expanded set of test cases provided on this web page. Again, you will use the Primetime static timing analysis software to determine the critical path delay of your circuit. Finally, you will complete your design by doing a computer layout of your circuit.
At this point you are probably aware of how many transistors your design requires. A manual layout of a 16-bit ALU would be a total nightmare. Instead, you will use an automatic placement and route software program called Encounter to layout your chip. This program is compatible with Cadence, so you will be able to export your Encounter layout to the Cadence layout after completion.
Top cell: alu
Input Signals:
A[15:0]: data input B[15:0]: data input CODE: control signal CIN: carry input
Output Signals:
C[15:0]: data output VOUT:nvalid output COUT: carry output
5-bit CODE[4:0]
logic operations (00---)
111: or => a OR b
011: xor => a XOR b
000: not => NOT a
101: and => a AND b
set condition operation (01---)
(a and b are signed numbers)
100: sle => if a <= b then c(15:0) = <0...0001>
001: slt => if a < b then c(15:0) = <0...0001>
110: sge => if a >= b then c(15:0) = <0...0001>
011: sgt => if a > b then c(15:0) = <0...0001>
111: seq => if a = b then c(15:0) = <0...0001>
010: sne => if a != b then c(15:0) = <0...0001>
otherwise, set c(15:0) = <0...0000>
arithmetic operation (10---)
101: add => signed addition (a+b -> c)
001: addu => unsigned addition (a+b -> c)
100: sub => signed subtraction (a-b -> c)
000: subu => unsigned subtraction (a-b -> c)
111: inc => signed increment (a+1 -> c)
110: dec => signed decrement (a-1 -> c)
shift operations (11---)
010: sll => logic left shift a by the amount of b
011: srl => logic right shift a by the amount of b
100: sla => arithmetic left shift a by the amount of b
101: sra => arithmetic right shift a by the amount of b
000: slr => rotate left shift a by the amount of b
001: srr => rotate right shift a by the amount of b
Logic shifts should shift in 0's and Arithmetic left shift should shift in 0's
Arithmetic right shift should shift in the most significant bit
Rotate left shift should shift out the most significant bit to the least significant bit
Rotate right shift should shift out the least significant bit to the most significant bit
Once you have completed your schematic design and static timing analysis of the alu, you will need to do a full layout of your functional circuit using Encounter auto place and route software. This is the final step for Lab 2.
Here is the tutorial for Encounter.
After you finish the apr. You need to perform post-apr timing analysis. Here is the detail how you can do it.
To turn in lab 2b, you must submit your merged netlist electronically, as well as print out a report and complete a demo for a TA.
For electronic submission, submit your netlist on Blackboard. To do this, go to Blackboard and sign in. Go to your class listing for VLSI. Click on "Assignment" go to LAB 2b part. Attach your netlist, and submit. Make sure that your file listing states explicitly that the netlist has been sent!
IMPORTANT: Title your netlist with your last name followed by underscore 2b. Example:
For Eric Quinnell's netlist for part 2b, the netlist would be titled: quinnell_2b
For the demo, use the 2b Report to check the material/printouts that you need to attach to your lab 2b Report. Include in this report:
The printouts of the Primetime reports, which includes the critical path of your ALU. (both pre and post APR scripts)
A paragraph explaining the strategies you used to optimize your delay and the architecture you use for your ALU.
A paragraph explaining your implementation of vout for the shifter.
The printout of the Encounter layout view with rulers on the sides as well as that portion of the log containing Verify Geometry and Verify Connectivity
Before you submit your design, please make sure that the top cell name and input/output pin names are same as required. (case sensitive)
IMPORTANT: Once you submit your file to Blackboard you won't be able to modify or re-submit your design. Please be very cautious before you submit it.
Part B takes 50% of total score in Lab 2
Functionality Correctness:25%
Speed: 15%
APR correctness: 5%
Lab Report: 5%
Penalty for late submission: 5% per working day. (maximum 25 %)
Bonus for early submission: 5% per working day. (maximum 10 %)