Abstract
Research in the areas of analog circuit fault simulation and test generation has not achieved the same degree of success as its digital counterpart owing to the difficulty in modeling the more complex analog behavior. This article presents a novel approach to this problem by mapping the good and faulty circuits to the discrete Z-domain. An efficient fault simulation is then performed on this discretized circuit for the given input test wave form. This simulator provides an order of magnitude speed up over tradition circuit simulators. An efficient fault simulator and the formulation of analog fault models opens up the ground for analog automatic test generation.
H. Zheng, A. Balivada, and J. A. Abraham, "A Novel Test Generation Approach for Parametric Faults in Linear Analog Circuits," Proceedings IEEE VLSI Test Symposium, April 1996, pp. 470-475.
N. Nagi and J. A. Abraham, "Hierarchical fault modeling for linear analog circuits," Journal of Analog Integrated Circuits and Signal Processing, Vol. 10, No. 1/2, June/July 1996, pp. 89-99.
Abstract
This paper presents a hierarchical fault modeling approach for catastrophic as well as out-of-specification (parametric) faults in analog circuits. These include both ac and dc faults in passive as well as active components. The fault models are based on functional error characterization. Case studies based on CMOS and nMOS operational amplifiers are discussed, and a full listing of derived behavioral faults models is presented. These fault models are then mapped to the faulty behavior at the macro-circuit level. Application of these fault models in an efficient fault simulator for analog circuits is also described.
A. Balivada, H. Zheng, N. Nagi, A. Chatterjee, and J. A. Abraham, "A Unified Approach to Fault Simulation of Linear Mixed-Signal Circuits," Journal of Electronic Testing: Theory and Applications, vol. 9, August 1996, pp. 29-41.
Abstract
The rapidly evolving role of analog signal processing has spawned off a variety of mixed-signal circuit applications. The integration of the analog and digital circuits has created a lot of concerns in testing these devices. This paper presents an efficient unified fault simulation platform for mixed-signal circuits while accounting for the imprecision in analog signals. While the classical stuck-at fault model is used for the digital part, faults in the analog circuit cover catastrophic as well as parametric defects in the passive and active components. A unified framework is achieved by combining a discretized representation of the analog circuit with the Z-domain representation of the digital part. Due to the imprecise nature of analog signals, an arithmetic distance based fault detection criterion and a statistical measure of digital fault coverage are proposed.
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