This research addresses techniques for increasing the testability of a design, particularly by modifications to the behavior. A novel technique of reconfiguring sequential circuits to appear combinational without using scan has been developed.
Another direction, in contrast with current approaches which seek to add testability features at the structural level after the design is essentially complete, makes the modifications early in the design process. The approach is to evaluate the testability of a design by analyzing the behavioral or register-transfer level description which is typically used in simulation models for design validation. This information is then used to propose testability features. In addition to addressing this important problem early in the design phase and decreasing the development cycle, we have found that the testability features often lead to much less overhead and performance impact because the optimizations during the synthesis process include these features.
G. Ganapathy and J. A. Abraham, "Selective Pseudo Scan - Combinational ATPG With Reduced Scan In A Full Custom RISC Microprocessor," Proceedings 30th IEEE/ACM Design Automation Conference (Best Paper Award) Dallas, Texas, June 14-18, 1993, pp. 550-555.
This paper presents a novel test generation technique, called Selective Pseudo Scan (SPS), which incurs very low overhead. SPS uses a commercial combinational ATPG tool to generate tests with high fault coverage by reconfiguring sequential circuits to appear combinational without inserting scan. Results of applying SPS to several complex control blocks of a full custom RISC Microprocessor, demonstrate its superiority compared to traditional full scan or partial scan in a full custom design environment.
P. Vishakantaiah, T. Thomas, J. A. Abraham and M. S. Abadir, "AMBIANT: Automatic Generation of Behavioral Modifications for Testability," Proc. IEEE International Conference on Computer Design, Cambridge, MA, October 3-6, 1993, pp. 63-66.