This research program aims to develop new and powerful self-test techniques applicable to large processor chips. While test generation and tester costs are beginning to dominate product costs, the available testability techniques are only applicable to small modules, are limited in their capabilities, and generally have an adverse impact on performance. This approach will exploit the inherent processing power of the chips by utilizing the functional modules and architecture-level behavior to implement self-tests with comprehensive fault coverage. Several different types of self-tests are being developed and evaluated using a hardware fault simulation engine. These include functional vectors modified for self-test, use of an extracted control flow machine to generated instruction sequences which exercise all the control behavior, and application of genetic transformations on the test sequences. The techniques will be validated by applying them to a variety of large benchmark circuits.