Computer Engineering Research Center
The University of Texas at Austin
The emergence of Computer Aided Design technology in the past decade has facilitated the design of highly dense and complex integrated circuits. There has been a continued effort to introduce new test methodologies which keep pace with the rapidly developing design technology and which do not increase the product cost or significantly degrade the performance of the design. Behavioral information about modules in a design is exploited by test engineers to handle the complex problem of test generation for large sequential circuits. However, automation of the process of exploiting behavioral information to facilitate test generation is in its infancy. This work involves the research and development of Automatic Test Knowledge Extraction Techniques called ATKET (pronounced as etiquette). These techniques use the structural and behavioral information in the VHDL description of a design to automatically generate test knowledge. High quality tests are obtained for a design using this test knowledge in conjunction with tests generated for modules in the design by a low level test generator that can target faults at the gate/switch level. Thus, ATKET makes automatic test pattern generation feasible for large sequential circuits while still targeting faults at the structural level. The extracted test knowledge also helps designers to consider testability during early phases of the design cycle, thereby facilitating design/synthesis for testability. The effectiveness of ATKET to facilitate generation of high quality tests and its capability to suggest behavioral modifications targeted at design/synthesis for testability is demonstrated using example circuits. The information generated using ATKET is also applicable in the areas of delay fault testing, critical path analysis, design verification and fault simulation. The results obtained using ATKET are very promising and indicate that the techniques are very effective and can lead the way towards test technology for next generation integrated circuits and systems.
P. Vishakantaiah, J. A. Abraham and M. Abadir, "Automatic Test Knowledge Extraction from VHDL (ATKET)", 29th ACM/IEEE Design Automation Conference, Anaheim, CA, June 8-12, 1992, pp. 273-278.
Behavioral information about modules in a design is exploited by test engineers to handle the complex problem of test generation for large designs. However, automation of the process of exploiting behavioral information to facilitate test generation is in its infancy. This paper introduces ATKET, an Automatic Test Knowledge Extraction Tool which automatically generates pieces of test knowledge by using structural and behavioral information in the VHDL description of a design. Results obtained from ATKET for a circuit which is difficult to test are presented.
P. Vishakantaiah and J. A. Abraham, "High Level Testability Analysis Using VHDL Descriptions," Proceedings The European Conference on Design Automation, Paris, France, February 22-25, 1993, pp. 170-174.
Tests generated for modules in a design may not be applicable from the design boundaries due to global constraints. This paper discusses high level techniques that can be used to analyze a sequential circuit and precompute useful information that reflects the controllability of inputs and observability of outputs of modules in the design. The information can then be used in conjunction with the tests generated for modules to obtain high quality tests for the design quickly. Results obtained for example circuits are presented to demonstrate these techniques.
P. Vishakantaiah, J. A. Abraham and D. G. Saab, "CHEETA: Composition of Hierarchical Sequential Tests Using ATKET," Proceedings IEEE International Test Conference, Baltimore, MD, October 17-21, 1993, pp. 606-615.
An approach to modular and hierarchical sequential circuit test generation, which exploits a top-down design methodology, uses high level test knowledge and constraint driven module test generation to target faults at the structural level, is introduced in this paper. Results obtained for several designs are provided to demonstrate the effectiveness of our approach and the need for high level knowledge along with global constraints while deriving sequential circuit tests.