The objectives of this research are to develop integrated solutions to the fundamental problems in test and verification and to serve as a conduit of information between research groups in verification and test, further stimulating novel solutions to problems in these two areas. As designs get larger every year, the two major problems faced by the semiconductor industry are to ensure that there are no bugs in the design and that the manufactured chips are defect-free. The program is unique in its emphasis on the application of formal techniques not only to verification, but also to test generation. A key direction of this research is the formulation of powerful abstractions which will reduce the state spaces which need to be searched during verification and test. This project is also developing an integrated set of software tools which will enable digital design engineers to formally verify the correctness of their designs and test the produced chip after manufacture.
J. Moondanos and J. A. Abraham, "Sequential Redundancy Identification Using Verification Techniques," IEEE International Test Conference, Baltimore, MD, September 22-24, 1992, pp. 197-205.
This paper describes techniques for the formal verification of sequential circuits, based on a rigorous theoretical background, that can be used to classify a single stuck-at fault in a synchronous sequential circuit as redundant or non-redundant, and to identify a non-redundant stuck-at fault as testable or untestable. The treatment of the synchronous sequential circuits is the most general possible, since the techniques do not require the existence of a reset state. Our programs can be used to successfully complement the use of traditional test generation techniques. Using the methods presented in this paper, we have been able to classify as redundant or non-redundant faults in the ISCAS-89 sequential circuits, that were either aborted or classified as untestable by test generation programs. We were also able to classify the non-redundant faults as untestable or testable.
R. Mukherjee, J. Jain, M. Fujita, J. Abraham and D. S. Fussell, "On More Efficient Combinational ATPG using Functional Learning." Proceedings 9th International Conference on VLSI Design, Bangalore, India, January 3-6, 1996, pp. 107-110.
Learning techniques like SOCRATES and recursive learning have greatly enhanced the technology of FAN-based ATPG. In this paper we present a test generation methodology for combinational circuits using functional learning, discuss application of novel functional information to enhance ATPG and present ATPG results on ISCAS 85 benchmark circuits. The test generation methodology combines the use of structural (topology) based analysis methods with the function representation techniques (such as BDDs).
D. Moundanos, J. Abraham and Y. Hoskote, "A Unified Framework for Design Validation and Manufacturing Test." Proceedings IEEE International Test Conference, Washington, D.C., October 21-24, 1996, pp. 875-884.
New approaches to address the difficult problems in test are necessary if its current status as a major bottleneck in the production of quality integrated circuits is to be changed. In this paper we propose a new direction for solving the test problem using powerful methods already employed for the formal verification of large circuits. More specifically, we will discuss how abstraction techniques can assist conventional ATPG tools when attacking hard to detect faults. The same abstractions can also be used in design verification to increase the level of confidence in a design following simulation, by providing a meaningful measure of the coverage achieved by the verification vectors. In this sense, our approach is geared toward providing a unified framework for design validation and manufacturing test.