Class meets, Thursdays, 6:30 - 9:30 pm, ECJ 1.312
Office: EER 4.874, Phone: (512) 471-8983
Office hours: Thursdays 4:00 - 6:30 pm, or by appointment
Office hours: Mondays 4:30 - 6 pm and Fridays 3:00 - 4:30 pm, in EER 0.810
Office hours: Tuesdays 3:00 - 6:00 pm and Thursdays 3:00 - 6:00 pm, in EER 0.810
VLSI Design, some object-oriented programming experience, computer architecture.
This course will cover the basics of verifying digital systems, from theory to industry practice. Laboratory exercises will deal with applications of the ideas in the lectures, and these will be based on verification tools currently used in industry.
The lectures will discuss the basics of verification, starting with logic, and include function representations based on binary decision diagrams, as well as satisfiability techniques. This will be followed by a comprehensive overview of assertion-based verification. Key topics then covered include formal methods of checking the equivalence of two designs, new directions in checking the equivalence of combinational and sequential designs, and fundamentals of temporal logic.
The fundamental concepts will be supplemented by examples of industry practice. These will include verification flows in industry, verification testbenches, Universal Verification Methodology (UVM), verifying memories, cache coherency, and semi-formal verification.
The class will also study model checking and its applications to property checking of real designs. Techniques for managing the complexity of verification using compositional techniques and abstractions, as well as novel techniques to expose subtle bugs will also be studied. The ideas will be applied to the verification of pipelined processors. New directions in verification will also be discussed.
Homework problems and laboratory exercises using commercial tools will be assigned to reinforce the concepts discussed in class. There will be one midterm exam in class on April 12. A team project, dealing with some aspect of verification, will be required in the class. Teams will present the results of their project to the entire class.
Lab 1 - Logic Equivalence Checking (LEC)
LEC is an important part of the front end design verification flow, because synthesis often optimizes the design to meet constraints, and there may be manual changes to the synthesized logic for testability, power and performance. These processes may change the logic inadvertently. The goal of this lab will be to check the logical equivalence between a RTL module and its synthesized version, and remove any logic bugs. Conformal LEC from Cadence will be used for this lab.
Lab 2 - Assertion Based Verification (ABV)
Assertion based verification is a methodology in which designers use assertions to capture specific design intent and, either through simulation, formal verification, or emulation of these assertions, verify that the design correctly implements that intent. In this lab, assertions must be added to a testbench to check for the correct operation of a protocol during simulation of the design. Mentor Questa will be the simulator used for this purpose.
Lab 3 - Universal Verification Methodology (UVM)
Universal Verification Methodology (UVM) is a powerful standardized verification methodology that was architected to be able to verify a wide range of design sizes and design types. In this lab, a UVM testbench will be set up in SystemVerilog for the given design under test (DUT). Using constrained random verification, the design will be tested for functional bugs. Mentor Questa will again be used for this lab.
Lab 4 - Formal Verification
This lab is designed to use a formal verification tool, JasperGold from Cadence, to check specified properties for all possible states of the design. An important takeaway from this lab is the ease with which properties could cause the tool to give vacuous results, take a very long time to complete the analysis, or time out, unless the specified properties are representative of the real design intent. Some recent advances in exposing subtle bugs in a complex design will also be studied.
Independent study of some aspect of verification, taking into account existing shortcomings of verification technology. Evaluate relevant publications and propose solutions to the problems addressed, or undertake a case study verifying a complex design.
Identify project teams, topic of project: March 22
One-page outline of project, deliverables: March 29
Project presentations in class: April 26 - May 3
Final project report due: May 11
|Jan. 18||1. Introduction to hardware verification and logic representations||Jacob Abraham||Lab. 1 assigned|
|2. An industry verification flow: verification at ARM||Alan Hunter, ARM|
|Jan. 25||3. Formal equivalence checking||Jacob Abraham|
|4. Finite automata and temporal logic||Jacob Abraham|
|Feb. 1||5. Assertion Based Verification||Harry Foster, Mentor||Lab. 1 due|
|6. System Verilog Assertions||Harry Foster, Mentor||Lab. 2 assigned|
|Feb. 8||7. Verifying clock domain crossings||Jacob Abraham|
|8. Symbolic trajectory evaluation, term rewriting||Jacob Abraham|
|Feb. 15||9. Verification testbenches||Nagesh Loke, ARM||Lab. 2 due|
|10. UVM basics||Nagesh Loke, ARM||Lab. 3 assigned|
|Feb. 22||11. Model Checking||Amit Goel, Apple|
|12. Application of ATPG algorithms and programmable hardware||Jacob Abraham|
|Mar. 1||13. Cache coherency, industry practise||Monica Farkash, NXP|
|14. Modeling, abstracting and verifying memories||Monica Farkash, NXP|
|Mar. 8||15. QED and Symbolic QED||Subhasish Mitra, Stanford|
|Mar. 11||Lab. 3 due, Lab. 4 assigned|
|Mar. 22||16. Semi-formal verification||Hari Mony, RealIntent|
|17. Sequential equivalence checking||Shaun Feng, Samsung|
|Mar. 29||18. Coverage, Data Mining and Machine Learning; Optimizing Test Constraints||Stan Sokorac, ARM|
|19. Techniques to extend tool capacity||Jacob Abraham|
|Apr. 5||20. Verification challenges: processor-based designs||Tse-Yu Yeh, Apple||Lab. 4 due|
|21. Verification Challenges: designs involving graphics processing units||John Coers, Apple|
|Apr. 12||22. Verification of analog/mixed-signal systems||Jacob Abraham|
|April 19||23. Am I ready to be a verification engineer?||Ram Narayan, ARM|
|24. New directions in verification||Jacob Abraham|
|April 26||Project Presentations|
|May 3||Project Presentations|
Homework 10% Midterm Exam 10% Laboratory Exercises 1 10% Laboratory Exercises 2, 3 & 4 15% (each) Project 25%
Allegations of Scholastic Dishonesty will be dealt with according to the UT Honor Code. Although we encourage you to study together, your designs and examinations you take MUST be your own work. Providing information to another student where prohibited, or obtaining information from another student where prohibited is considered cheating. This includes the exchange of any information during an examination and any part of your design for the laboratory exercises. Allowing another student to read something on your paper during an examination is considered cheating. In fact, leaving information unprotected so it can be compromised by another student is considered cheating. This includes sheets of paper lying about in your dorm room, and computer files that are not properly protected.
The University of Texas at Austin provides, upon request, appropriate academic adjustments for qualified students with disabilities. who may request appropriate academic accommodations from the Division of Diversity and Community Engagement, Services for Students with Disabilities, 471-6259, http://ddce.utexas.edu/disability/accommodations-and-services/
By UT Austin policy, you must notify me of your pending absence at least fourteen days prior to the date of observance of a religious holy day. If you must miss a class, an examination, a work assignment, or a project in order to observe a religious holy day, you will be given an opportunity to complete the missed work within a reasonable time after the absence.
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