Jayanta Bhadra's Homepage Jay Bhadra's Homepage Austin TX

Jayanta (Jay) Bhadra

Hardware System Design and Verification World-Wide Central R&D Manager NXP Semiconductor

Adjunct Associate Professor, Computer Engineering, The University of Texas at Austin

Spring Semester: EE 382M-11, Verification of Digital Systems (graduate level class with Unique number 17270)

Personal

Many thanks to my PhD advisor, Prof. Jacob Abraham, and my lab CERC for hosting this page since 1997.
Thanks also to Andrew Kieschnick for helping me with various web issues through these years.


For UT related communication: jay at cerc dot utexas dot edu
For all other communication: full first name dot last name at nxp dot com
Jay Bhadra's Homepage