Jayanta Bhadra's Homepage Jay Bhadra's Homepage Austin TX

Jayanta (Jay) Bhadra

Adjunct Associate Professor, Computer Engineering, The University of Texas at Austin

Verification Tools/Flows R&D Manager and World-Wide Technical Lead, Freescale Semiconductor Inc.

Journal of Electronic Testing: Electronic Testing: Theory and Applications (JETTA)
Special Issue on Design Verification and Testing Challenges in Future Microprocessor and SOC Designs
(CALL FOR PAPERS)

Spring 2012: EE 382M-11, Verification of Digital Systems (Unique number 16873, graduate level)

Course Webpage (please see blackboard for homeworks and labs using your UT-EID)
Formal Verification of Hardware: reviews and surveys
Publications

Announcements from conferences/workshops where Jay is involved in the capacity of a Technical Program Committee member:

IEEE International SoC Conference (SOCC), September 2012: website
VLSI Test Symposium (VTS), April 2013: website
International Symposium on Quality Electronic Design (ISQED), March 2013: website
International Workshop on Microprocessor Test and Verification (MTV), December 2012: website

Personal

A short Bio
Photography: please email Jay if you want access. A small glimpse can be found here.

Many thanks to my advisor, Prof. Jacob Abraham, and my lab CERC for hosting this page since 1997. Thanks also to Andrew Kieschnick for helping me with various web access issues.

For UT related communication: jay at cerc dot utexas dot edu

For all other communication: full first name dot last name at freescale dot com

Jay Bhadra's Homepage