Citations and related work
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Some papers that cited our work (potentially current as of August 2006)
- D. V. Lettnin,
Verification of Temporal Properties in Temporal Software,
Ph.D. Dissertation, University of Tubingen, Germany, 2009.
- I. Parulkar and I. Turumella, Comprehensive Approach to
High-Performance Server Chipset Debug
IEEE Design & Test of Computers, Volume 26, Issue 3, May-June 2009
Page(s):70 - 77.
- H.-Z. Chou, I.-H. Lin, C.-S. Yang, K.-H. Chang, S.-Y. Kuo,
Enhancing Bug Hunting Using High-Level Symbolic Simulation,
Great Lakes Symposium on VLSI, 2009.
- T. Lv, J.-P. Fan, X.-W. Li and L.-Y. Liu,
Observability Statement Coverage Based on Dynamic Factored
Use-Definition Chains for Functional Verification,
Journal of Electronic Testing: Test Automation, Vol. 22, No. 3, June
2006.
- V. Vedula, F. Andersen, J. Abraham, Taming the Complexity
of STE-based Design Verification Using Program Slicing, IEEE
International High Level Design Validation and Test Workshop, 2006.
- L. Lingappan, S. Ravi, N. K. Jha, Satisfiability-Based Test
Generation for Nonseparable RTL Controller-Datapath Circuits, IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol. 25, No. 3, March, 2006, pp. 544-557.
- M. Hatzimihail, M. Psarakis, G. Xenoulis, D. Gizopoulos, A.
Paschalis, Software-Based Self-Test for Pipelined Processors: A Case
Study, IEEE International Symposium on Defect and Fault Tolerance in VLSI
Systems, 2005, pp.
- A. Tate, V. M. Vedula, J. A. Abraham, Program Slicing of
Structural Netlists for Efficient Sequential Test Generation, Latin
American Test Workshop, 2003.
- C.-J. H. Seger, R. B. Jones, J. W. O.Leary, T. Melham, M. D.
Aagaard, C. Barrett, D. Syme, An Industrially Effective Environment for
Formal Hardware Verification, IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, Vol. 24, No. 9, September 2005, pp.
1381-1405.
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Jeffry T. Russell, Slicing and Characterizing Typical-Case Behavior
for Component-Based Embedded Systems, Ph.D. dissertation, The
University of Texas at Austin, 2005.
- V. Viswanath, J. A. Abraham, W. A. Hunt, RTL Annotations for Low
Power Microprocessor Design, IBM Austin Conference on Energy-Efficient
Design, 2005.
- D. Ferrao, G. Wilke, R. Reis, J. L. Guntzel, Improving Critical
Path Identification in Functional Timing Analysis, Symposium on Integrated
Circuits and Systems Design, 2003.
- S. Vasudevan, V. Viswanath, J. A. Abraham, Dedicated
Rewriting: Automatic Verification of Low Power Transformations in RTL,
International Conference on VLSI Design, January 2009.
- S. Vasudevan, V. Viswanath, J. A. Abraham, Efficient
Microprocessor Verification using Antecedent Conditioned Slicing,
International Conference on VLSI Design, January 2007.
- S. Vasudevan, E. A. Emerson, J. A. Abraham, Improved Verification
of Hardware Designs through Antecedent Conditioned Slicing, International
Journal on Software Tools for Technology Transfer, Vol. 9, No. 1,
February 2007.
- K. Kambe, T. Iwagaki, M. Inoue, H. Fujiware, Efficient Constraint
Extraction for Template-Based Processor Self-Test Generation, Asian Test
Symposium, 2005.
- T. Li, Y. Guo, S. Li, An Automatic Circuit Extractor for RTL
Verification, Asian Test Symposium, 2003.
- M. Boule, Z. Zilic, Incorporating Efficient Assertion Checkers
into Hardware Emulation, International Conference on Computer Design,
2005.
- M. B. Dwyer, J. Hatsliff, M. Hoosier, V. Ranganath, Robby, T.
Wallentine, Evaluating the Effectiveness of Slicing for Model Reduction of
Concurrent Object-Oriented Programs, Tools and Algorithms for the
Construction and Analysis of Systems, 2006.
- M. Alberti, M. Gavanelli, P. Mello, F. Chesani, E. Lamma, P.
Torroni, On the automatic verification of interaction protocols using
g-SCIFF, Technical Report no. DEIS-LIA-004-04, University of Bologna.
- K. Uday Bhasker, M. Prasanth, V. Kamakoti, K. Maneparambil, A
Framework for Automatic Assembly Program Generator (A2PG) for Verification
and Testing of Processor Cores, Asian Test Symposium, 2005.
- N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, Y. Zorian,
.Application and Analysis of RT-Level Software-Based Self-Testing for
Embedded Processor Cores, International Test Conference, 2003, pp.
431-440.
- V. M. Vedula, W. J. Townsend, J. A. Abraham, Program Slicing for
ATPG-Based Property Checking, International Conference on VLSI Design,
2004.
- V. Viswanath, J. A. Abraham, W. A. Hunt, Automatic Insertion of
Low Power Annotations in RTL for Pipelined Microprocessors, Design,
Automation and Test in Europe, 2006.
- M. Pandey, R. E. Bryant, Efficient Synthesis of Ternary State
Machines from STE Assertions, International Workshop on Microprocessor
Test and Verification, 2002.
- J. Zeng, M. S. Abadir, J. A. Abraham, False Timing Path
Identification Using ATPG Techniques and Delay-Based Information, Design
Automation Conference, 2002, pp. 562-565.
- M. Alberti, M. Gavanelli, E. Lamma, F. Chesani, P. Mello, P.
Torroni, A Computational Logic-Based approach to security protocols
verification, and its application to the Needham-Schroeder Public Key
authentication Protocol, Technical Report, University of Ferrara.
- R. Kaivola, K. Kohatsu, Proof Engineering in the large: Formal
Verification of the PentiumŪ floating-point divider, International Journal
on Software Tools for Technology Transfer, Vol. 4, No. 3, May 2003.
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From Google Scholar
For more papers, try this link. Thanks for your interest, good luck.
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Impact factors of selected conferences/journals
For impact factors, try here.
Last updated: August 2006.
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