In lab1, most of your job is done by cadence tool. Here is a tutorial how you can go through all the process
First of all, you should create a directory under your home directory, say "vlsi1". Login to sunapp machine, and type following steps in your terminal:
cp /home/ecelrc/students/jpak/public_html/lab1_files/cds.lib vlsi1/.
cp /home/ecelrc/students/jpak/public_html/lab1_files/cdsinit vlsi1/.cdsinit (Be careful! The copied file should have '.' in front of the original file name. )
cp /home/ecelrc/students/jpak/public_html/lab1_files/lib.defs vlsi1/.
chmod 700 -R vlsi1 (IF you ignore this THEN you will be equally responsible if someone copies from your lib)
resetenv (They will ask you choose a number. Select number 1.)
Now, log out and you finish the setup procedure. You have to do this for only ONCE. Next time you are using the Cadence tool, you can skip this step,
From here, you need to type every time before you use cadence.
Login to sunapp machine. Type in your home directory
Move to vlsi1 directory and type following.
module load cadence
module load mentor/calibre
Now type in cadence command in your vlsi1 directory.
The following window would appear on the screen:
We refer to this window "CIW". CIW displays Cadence log file "CDS.log" stored in your "vlsi1" directory. When you use a specific Cadence tool (e.g. Virtuoso) and run a task (e.g. DRC), the result is sometimes displayed in the CIW. So you should check back on this window quite often.
Your Cadence designs (schematic, layout, ...) are organized in the form of libraries. You can go to Tools->library manager to invoke the library manager.
At any time when you run into any problem, you can always read the Cadence document by invoking specific documents through the Help menu.
CIW and Library Manager window are
the two most important windows of Cadence tools. CIW shows the log information;
library manager helps you manage your designs which are generally organized in a
number of cells. Every time when you start Cadence tools, you would always want
to start a library manager from CIW as well.
When starting a design in Cadence, the first thing to do is to create a library where you can store your designs. Every Library is associated with a technology file and it is the technology file that supplies all the color maps, layer maps, design rules, extraction parameters required to view, design, simulate and fabricate your design.
Start a Library Manager
In CIW, click on Tools->Library Manager. The following window appears. (You may have different library names depending on your cds.lib file)
In Library Manager window, enter the name of library (example shown: Lab1) as shown in the following window where you expect to store your own designed cells.
Just, click OK button in the following window.
Attach this library to an existing technology (example shown: NCSU_TechLib_FreePDK45) so that the Cadence tools would know the technology specifics of your design (like SPICE models, DRC rules, ERC rules, etc.)
You can also use "compile tech library". This creates a local copy of the technology library in your run directory, thus it is not very efficient in the sense that every use has a copy of an identical library. It is also not very flexible in the sense if there is any change made to this technology library, each user has to update his copy of the compiled tech library. Because of these two reasons, we prefer "attach to existing tech library" to "compile tech library".
Now your library manager window will pop up
Not only you have created a library "Lab1" of your own, but you have also included its associated technology library "NCSU_TechLib_FreePDK45" in your library path.
At this point, you have created a library (in the example "lab1") to store your design and can start the design process. For a full custom design, the process begins by creating a schematic. Then we simulate this design to verify the correctness of its functionality and explore its switching behavior in order to optimize the performance. Only after this is done, we will start the layout of the design.
In your Library Manager window, click on the File->New->Cellview. A pop-up dialogue box appears. Click on the library name button and select "lab1". The View Name will automatically change to "schematic". If it is not schematic, you can change it by clicking the View Name field. Enter the name of the cell you wish to design in Cell Name. For the tutorial case, we design an inverter.
This will pop-up an empty Schematic Editor Window. We will talk about how to create an inverter in this schematic window in the following steps. We will start by adding an instance of NMOS and an instance of PMOS.
To place an instance, e.g. an NMOS device, in your schematic, activate the schematic window, then click on Create->Instance (or type i). The "Add instance" dialogue box appears together with the "Component Browser" dialogue box. (In case the "Component Browser" does not appear, click on browse in the "Add Instance" dialogue box to start it.)
NOTE: For the nmos transistor, you must change the parameter "Width" to 100nM for the lab1 assignment.
In "Component Browser" window, choose NCSU_Devices_FreePDK45 in a library section. Choose NMOS_VTL as your NMOS device, and select symbol in a view section. To place the instance, activate the schematic window and click the left mouse button to put the instance at the place desired.
Note in Cadence schematic composers and layout editors, a command will not terminate unless the user cancels it or the user starts a new command. In this case, you can see another instance is ready to be placed right after you placed the first instance. To terminate the current operation (which is "add instance" in this case), press ESCkey on the keyboard. In fact, you can always cancel the current operation in schematic or layout editors by pressing ESC key.
To set the property of the instance that you just placed or any object in your schematic or layout design, select the object by clicking on it and then go to "Edit->properties->Object..." (or by typing q). An object properties editing form will pop up.
Change the width or length of the gate to the desired value. Following the same techniques, we can add an instance of PMOS transistor.
NOTE: For the pmos transistor, you must change the parameter "Width" to 200nM for the lab1 assignment.
To connect the PMOS and NMOS devices or any electrically connected devices, click on Create->Wire(narrow) in the schematic window (or type w). Click at the terminal where the wire starts and click at the terminal where the wire ends, a wire will be automatically added. If you are not satisfied with the automatic wiring, you can remove the wire and reroute it manually. This time, instead of clicking at the terminal where the wire ends directly, you can click the left mouse button whenever you want to change the wire direction.
If you want to stop the wire somewhere instead of connecting it to a terminal, double click your left mouse button and a dangling wire is created. In general dangling wire should be avoided, however, in some cases (like you want to label this wire or add a pin to this wire), a dangling wire makes sense.
For any cell, we have to specify its input/output behavior. We can achieve this through adding the pins for its input and output. For some global wires (like vdd and gnd), we can simplify the I/O of the schematic by adding a label to each one of them.
Click on "Create->Pin..." (or type p) in the schematic window, the following dialogue box would appear.
For an input pin, Choose the Direction to be input. Specify the Pin Names (inv_in in the example). Activate the schematic window and click on the left mouse to put the pin. Similarly we can put an output pin (inv_out in the example) to the output of the cell.
<***For info only*****>Adding labels to the wires is similar to adding pins. Click on "Create->Wire Name..." (or type l) in the schematic window, the following dialogue box would appear. You can specify a name for each wire, but we generally only add labels for those global wires like "vdd" or "gnd". In order to denote a global wire name, you have to add a "!" after the wire name (vdd! in our example).
After the design has been completed, click on "File->Check and Save" to check and save your designs, or use hotkey F8.
Check the CIW window to see if there is any errors in your designs.
The following image shows the completed design of inverter. Please note that the width of pmos in this image is set to 200n and width of nmos is 100n. Also check that the bulk node (Body bias) should be connected to vdd for pmos, gnd for nmos.
Please note that cadence automatically labels internal nodes (like the ones seen above in white color, you do not have to explicitly label those ).
Symbols are useful when
the schematic design is done hierarchically. At a higher of level of
abstraction, we would like to use a symbol to replace the details of a cell.
Because of this, a symbol of a cell design should define all the inputs and
outputs of that cell.
There are two ways to create a symbol. If you have a schematic design already, you can create its symbol right from the cell. If you don't have a schematic design yet and you want to create a symbol for the cell, you can start from scratch.
Create a symbol from an existing schematic
Click on Create->Cellview->From Cellview menu in the symbol edit window, a pop up dialogue box will appear. We can use the default setup in this window to create the symbol.
This will pop-up another window that contains a default symbol picture. It has a red box that encloses the green colored inverter symbol. This red box defines the actual size a symbol will occupy, if you were to use this inverter in another design. You can change the size of this box. It is good custom to exactly fit the symbol within the red box. The red square dots indicate the pin connections. [@InstanceName] and [@PartName] are display variables, which you may delete or keep. The following picture shows the symbol.
If you don't like this rectangular symbol that is automatically created by the tool, you can create a symbol of you own.
As long as we know the inputs and outputs of a cell, we can create a symbol for it. We can either draw the lines and arcs ourselves (which is pretty self-explanary and the hot keys are very much similar to the schematic composer window). The final symbol is shown below.
We use Verilog-XL to simulate our designs at logic level. In another word, we
can only check if our design if functionally correct by using Verilog simulation. We will not be able to know, for
example, the transient behavior of the circuit. Thus we will not be able to know the delay and timing information for the circuit. To simulate the transient behavior, we should use Cadence SPECTRE which is very similar to SPICE.
Still, Verilog simulation is very important. A circuit has to be verified to be functionally correct before we look into its transient behavior. This section talks about how to write a Verilog "testbench" for the schematic we created and simulate its behavior. In order to use this tool, only minimal knowledge of Verilog is required (basically on how to supply the stimuli during the simulation).
In the schematic design window, click on Launch-> Simulation->Verilog-XL to start the verilog-XL. A pop up dialogue box will appear.
Use the default settings would create a directory named inverter.run1 under the cadence run directory for the verilog simulation. We can specify another path if needed. In this case, we use the default settings. Now a Verilog simulation window appears:
For the first run, since we do not have a stimulus file yet, we click on Yes. A template file named testfixture.verilog has been created for us and a new pop up window appears.
Choose testfixture.verilog as our stimulus file, and click OK. Now we can modify this file to supply the stimuli during the simulation. Use any text editor(e.g. gedit, vi, emacs, ...) to edit this 'textfixture.verilog' file under the simulation directory (~/vlsi1/inverter.run1/testfixture.verilog in this example). The orginal file is shown in the left window below. Now we create a square wave for the input by letting inv_in to be "1" at 100ns and "0" again at 200ns. The modified simulation file is shown in the right window below. After modification, save your verilog file.
Now click on Simulation->Start Interactive in the simulation window. The simulation initiates. Click on Simulation->Continue to complete simulation. The simulation window looks like below when it completes.
If we run into any problem in the simulation, we can check on the si.log in the simulation directory (~/vlsi1/inverter.run1 in this example.)
We can use a tool called "Simvision" to view the results in a waveform format. Click on Debug->Utilities->View Waveform in the simulation window. The waveform window appears.
In the waveform tool window, click on File-> New-> Design Browser, a design browser window pops up. Click on test in the left part of the design browser window. Select all the signals interested (in this example both inv_in and inv_out) by clicking on them right part of the design browser window. Finally click on "Send To Waveform" button, second button from left between 7 buttons in the upper right of the window, to display the waveforms in the waveform window.
Spectre is a Cadence version of the SPICE circuit simulator. The syntax of Spectre is compatible with SPICE simulation. By Comparison to Verilog-XL, Spectre lets you simulate transient behavior of your circuit at the transistor level. In this section, we will perform a transistor level simulation for the inverter schematic and observe its transient behavior.
In the schematic design window, click on Launch-> Simulation->Spectre to start the Spectre. Unlike many other tools, there is no pop up window. Instead, You will see an added item "spectre" on the menu of the schematic window.
In the schematic design window, click on Spectre-> Initialize.... A pop up window appears like below. We can specify the location for the spectre simulation directory. The default path for the created directory is right under your Cadence run directory.
Click on "OK" to accept the directory and another window pops up like below. Click on "OK" to accept the default setup.
Before we do the simulation, we should first generate the netlist for our circuit. Click on Spectre->Netlist and Simulate... and the following window will pop up.
In Run Actions field, choose ONLY netlist and create run file. Click on "OK" to start netlist extraction and run file creation. After a while, a message box would pop up to tell you if it is successful or not. In case there is an error, check si.out and si.log in the simulation directory to figure out the reason.
Now we have two ways to create a simulation file. One way is to supply the data through menu and dialogue box. The other way is to edit the simulation file using a text editor. We will only talk about the second approach.
Now go to the simulation directory (in this example ~/vlsi1/spectre.run1). Edit the si.inp file. Here is how the file looks like. We can see the netlist of the inverter.
To simulate the transient behavior of an inverter, we hope to add a voltage source to its input and a capacitor at its output so that we could observe the output voltage change in the time domain. The equivalent circuit is shown below.
We need to modify the spectre simulation file for the simulation. Here is one modified si.inp file. You can take this file as reference and add the lines to your si.inp file.
Also, See the detailed Spectre tutorial from this link :spectreuser.pdf
The modification has been done in the following steps:
- Include the model files(NMOS_VTL, PMOS_VTL) for the transistors
The 2 model files are all located in /usr/local/packages/cadence_2007/FreePDK45/ncsu_basekit/models/hspice directory.
- Add the capacitor at the output(shown as COUT)
- Add voltage sources
Vdd(=1V) and Gnd are two DC voltage sources that specify the voltage level of the global variable we defined earlier vdd! and gnd!. Vin actually specifies the curve for the input voltage. It is a PieceWise Linear voltage source (pwl).
- Specify the analyses method(shown as tran1 in si.inp)
we simulate the transient mode starting from 0ns to 5ns and stops at every 0.1ns
Click on Spectre->Netlist and Simulate... again and the same window appeared earlier when we generated the netlist and run file will pop up. This time, in Run Actions field, choose ONLY simulate. Click on "OK" to start spectre simulation. After a while, a message box would pop up to tell you if it is successful or not. In case there is an error, check si.out and si.log in the simulation directory to figure out the reason.
Click on Spectre->Waveform tool and three windows Results Browser, Calculator and Graph window will pop up.
Go to the Results Browser, double click on tran1-tran (whichever you have named it in your modified si.inp file).
The directory spans and the signals will appear in the Results Browser.
Double click on the inv_in in the Results Browser, then the waveform would appear in the Graph Window, you can separate & plot, etc.
The corresponding wave form is now shown in the waveform Graph Window.
Repeat to get the waveform for inv_out. Now the waveform window displays the curve for both inv_in and inv_out. Click on the 4th icon on the upper hotkey bar of the waveform Graph Window, which says Strip Chart Mode. Now the waveforms are displayed separately like below.
By now, we have already created the schematic and have simulated our design with verilog-XL . The next step in the design process is to create the layout for the circuit. A layout is basically a drawing of the masks from which your design will be fabricated. Therefore, layout is the most critical step in the design process because it determines whether your design is finally going to be working or not.
There are two ways to draw layout. You can create a layout from scratch. You will have more flexibility with it, but it takes more time. You may also create a layout using Layout XL, which will be much faster. Following is a tutorial how you can create layout by LayoutXL.
This opens up the virtuoso XL Layout editing window and the Layer select window (LSW)
In order to show the raw netlist , In your Layout window click Connectivity -> Generate -> All from Source
make the following changes in the layout generation form.
Change default in Layer/Master to metal1 ( or the corresponding pin metal layer in big designs M2/M3....)
Your width should be 0.065
Then Click the Apply button. This button will change all your defaults of the pin type layer.
Select text display for pin label shape (you can reduce the text font size in 'Pin Label Options'.)
Make sure your options same as the following figure.
click OK .( Bottom center).
Now , change the display setting of your layout window click options-> display.
Reconfig 'Display Controls' as shown in the following snapshot;
Then change your X Snap and Y Snap spacing to 0.0025 and Apply -> OK. (This is important so as to reduce the DRC errors).
Now we start the actual Layout Editing. The Hotkeys are:
Here is a tip to build ntap which is the substrate (bulk) terminals for the pmos. Ntap consists of nwell + active + nimplant + contact to connect substrate and vdd with ohmic contact. The contact should be connected by vdd. In a similar way, ptap consists of pwell + active + pimplant + contact ( to gnd ).
The sample layouts of nmos, pmos, ntap, ptap are provided in TR_TAP library. See more detailed information to start a layout using TR_TAP library: (Layout 101 - also linked on the right side of 'Lab Detail' page.).
Also,all design rules are posted in wiki : http://www.eda.ncsu.edu/wiki/FreePDK45:Contents
Please read FAQs regarding the detailed information regarding design rules. (FAQs). 'FAQs' is linked on the right side of 'Lab Detail' page.
After making the connections, the drawing will look like this (or some variant of this as the example puts little emphasis on area optimization in the current layout).
Before saving the design, we hope to make sure that the design has conformed to the design rules. As careful as one might be, it is very hard for a designer to avoid all the design rule errors. To perform the design rule checking, click on Calibre -> Run DRC... in the layout window. A pop up dialogue box will appear ( Popping up a box takes more than 30 seconds ). Press cancel button for the following box.
After closing the above box, the following window will be presented. Enter the rule file for DRC as shown in the following line. DRC rule file is a textfile, so you can open and check the design rule specifications.
DRC rule file : /home/ecelrc/students/jpak/public_html/lab1_files/calibreDRC.rul
Press inputs button and make sure that Export from layout viewer is marked. Then, press "Run DRC" button.
DRC takes at least one minute. The following window will appear first.
Sometime after, you will see the following window. The number of results means the number of DRC errors. Thus, make sure that the error is zero before you proceed to LVS. If there is no DRC error, the DRC window looks like the following window.
After the cell has been checked, click on File -> Save... in the layout window to save your design.
We have created the layout as well as the schematic for an inverter, but how do we know they represent the same circuit? One way to verify this is by generating a circuit netlist from the layout and comparing it with thess netlist for the schematic.
In the layout window, click on Calibre -> Run LVS....A pop up dialogue box will appear ( Popping up a box takes more than 30 seconds ). Press cancel button for the following box.
After closing the above box, the following window will be presented. Enter the rule file for LVS as shown in the following line. LVS rule file is a textfile, so you can open and check the LVS rule specifications.
LVS rule file : /home/ecelrc/students/jpak/public_html/lab1_files/calibreLVS.rul
Press inputs button and make sure that Flatand Layout vs Netlist is marked. Mark Export from layout viewer. Press netlist and markExport from schematic viewer as shown in the bottom side. Then, press "Run LVS" button.
LVS takes at least two minutes. The following window will appear first. If the message looks like the following window, LVS is finished. However, if LVS reports "incorrect", you need to find the difference between schematic and layout.
Sometime after, you will see the following window. Make sure that Designs are matched. If there is no LVS error, the window looks like the following.
We are going to extract the parasitic capacitance and resistance from the layout information. In order to have the extraction, a Parasitic Extraction(PEX) should be performed. Click on Calibre -> Run PEX in your layout window. A pop up dialogue box appears. (Poping up a box takes more than 30 seconds). Press Cancel button for the following box.
After that, the following box appears. Enter the rules file path for extraction (xRC)
xRC rule file : /home/ecelrc/students/jpak/public_html/lab1_files/calibrexRC.rul
Click on inputs->Layout and check "Export layout viewer".
And then, click on inputs->Netlist and check "Export from schematic viewer".
lastly, click on outputs->Netlist and check "View netlist after PEX finishes".
Click on Run PEX and wait for a while. After that, you can see the result. you should check "no xRC error" on the Transcription.
You can also get the PEX netlist window.
This netlist includes two more files. You can find the three output files in your working directory; the format of the outputs from the extraction is HSPICE. In this example, the three files are inverter.pex.netlist , inverter.pex.netlist.INVERTER.pxi, and inverter.pex.netlist.pex.
In part A, submit the output files of those three types :*.pex.netlist, *.pxi and *.pex
With the three outputs of the extraction, you can have post layout simulation with HSPICE.
To execute HSPICE simulation
Type "module load cadence" in the terminal (for Library)
Type "module load synopsys/hspice" in the terminal (for HSPICE)
Type "module load syn/cosmos" in the terminal (for CSCOPE)
You may have *.pex.netlist, *.pxi and *.pex in your working directory.
Make your hspice netlist file with those three files.Example file link: test.sp Here is a brief HSPICE tutorial file.
( Don't follow the 'Setting up Account' section in page 2 of this tutorial.Just use this tutorial to make a .sp file to simulate.)
You can find more 'really brief' tutorial for this lab on the 'extra clarification for lab1' on the right side of the lab detail page.
Please read the sample test.sp carefully. Be aware of that the pin order in the test.sp should be same as the one in *.pex.netlist.
With test.sp file, you can run HSPICE.
Type "hspice test.sp >! test.log" in your terminal
If the sp file has error, you will have "abort" message in your terminal. In this case, you can find the source of the error through the test.log file.
After you get " ***** hspice job concluded" message from your terminal, type "cscope".
In the CosmosScope(cscope), click on file->open->plotfiles
Open your *.tr* file.
You have two more pop up window. In the window, select inv_in and inv_out and click the plot button.
You will see the waves in the Graph window. Please adjust the simulation time to be long enough, to see the whole transition of output waveform until output is fully charged or discharged.
To mesure the signal, click on menu tool->measurement tool.
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