Jae-Seok Yang

ADDRESS: 13211 Kenswick Dr. Austin, Tx, 78753

CELL PHONE: 510-684-4517

E-mail: jsyang@cerc.utexas.edu, jsyang74@gmail.com

 

Profile

More than 6 years of experience in computer aided engineering for ASIC and Memory. Strong background in programming with C/C++/OpenAccess as well as cell-based/full-custom design flow/tools. Experienced in various projects from design methodology development to successful EDA algorithm/tool development. Current interest is CAD for 3D-ICs, Double patterning lithography, DFM.

 

Education

l   University of Texas at Austin

Ph.D. in Electrical and Computer Engineering, from Jan. 2008

Research advisor: Prof. David Pan

l   University of California at Berkeley

M.Eng. in Electrical Engineering, Dec. 2007

Thesis: Cross-Talk variation assessment and statistical peak noise analysis

l   Sogang University at Seoul, Korea

B.S. in Electrical Engineering, Feb. 1997

Thesis: The implementation of the dynamic power estimator by means of transition probability calculation

 

Research experience & Background

Ph.D. Researcher, University of Texas at Austin                                                        2008-present

l  Study on DFM and physical design

l  Double patterning aware CAD algorithm development

: Overlay aware timing analysis methodology, Layout decomposition algorithm development for double patterning

l  Teaching assistant : VLSI-I (Spring 2009)

l  3D-IC DFM

Student Researcher, University of California at Berkeley                                                   2005-2007

l  Study on DFM and semiconductor processing focused on lithography simulation and RET

l  Statistical peak noise analysis flow

: Crosstalk variation assessment using test structure, device length variation model considering spatial correlation, combining interconnect variation caused by lithography and CMP process

CAE Engineer, Samsung Electronics Co., Ltd., HwaSung, Korea                                                          1999-2005

l  Signal integrity related experience

¨ª  Crosstalk noise analyzer development at transistor level and application to memory and LDI(LCD Driver IC)

: Coding the entire program with C language including DSPF parser, CCC(Channel connected component, construction, vector generation for the worst peak noise, aggressor alignment, spice deck generation, noise propagation criterion, parasitic victim filtering, small aggressor pruning, and false victim filtering

: Successful applications of more than 10 LDI chips and 70 memory chips including DRAM, Graphic DRAM, Nand FLASH and SRAM

¨ª  Gate level signal integrity flow setup

: Automatic evaluation program development to compare the accuracy for the various commercial tools and different flow in terms of timing and noise

: CeltIC(Cadence) evaluation and design flow setup

l  Timing analysis and optimization experience

¨ª  Coupling aware delay calculator development for gate-level timing analysis

: Coupling capacitance modeling for a delay change, false aggressor elimination using temporal and functional relationship, driver modeling as a voltage source and resistance, study and evaluation on reduced order model such as AWE and PRIMA

¨ª  Static timing analysis development at transistor level & optimization using transistor sizing

: Latch recognition, technology file generation, concurrent gate sizing and path sensitization (Avoiding the false path optimization), Elmore delay modeling implementation

¨ª  Timing optimization with the rich cell generation using ZenTime (Zenasis), and automatic cell generation

: Rich cell generation flow evaluation using ZenTime, 300 cell à 700 cell (ARM speed 8% up)

: Automatic transistor sizing tool development for achieving the given timing specification

l  Power management experience

¨ª  Leakage current estimator development based on wafer measurement

: Leakage variation assessment, stacking effect consideration, transistor state determination during sleeping mode, finding the hottest cell or block

l  Etc.

: Epic tool (PowerMill, TimeMill, PathMill) management, automatic output comparison environment between old and new version, license management

 

Honors and Awards

l  2010  The best paper nomination at ASP-DAC 2010 DFM track

¡°A New GraphTheoretic, MultiObjective Layout Decomposition Framework for Double Patterning Lithography¡±

l  2003  The best paper award in Samsung CAD/CAE Conference

¡°Development of SI sign-off flow for full-custom design¡±

l  2002  Semiconductor Society¡¯s best paper award in the SOC Design Conference

¡°A true aggressor determination method for accurate crosstalk analysis using functional relationship¡±

l  2002  The best paper award in Samsung CAD/CAE Conference

¡°Development of EZWare's post-layout analysis and application of memory circuits¡±

l  2002  The best paper award in the Samsung Semiconductor Technical Conference

¡°Cubic-SI : coupling aware delay calculator¡±

l  2002  The best paper award in the Samsung Semiconductor Technical Conference

¡°An efficient true aggressor determination method for cross-talk analysis in UDSM design¡±

l  1997  Samsung Scholarship award for M.S. degree

 

Publications

< International Publications >

l  Jae-Seok Yang, Katrina Liu, MinSik Cho, Kun Yuan and David Z. Pan, ¡°A New GraphTheoretic, MultiObjective Layout Decomposition Framework for Double Patterning Lithography¡±, ASP-DAC 2009, Best Paper Nomination (To appear)

l  David Z. Pan, Jae-seok Yang, Kun Yuan, Minsik Cho and Yongchan Ban, ¡°Layout Optimization for Double Patterning Lithography¡±, ASICON, 2009 (Invited paper)

l  Kun Yuan, Jae-Seok Yang and David Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization", International Symposium on Physical Design (ISPD), San Diego, March 2009

l  Jae-Seok Yang and David Z. Pan, "Overlay Aware Interconnect and Timing Variation Modeling for Double Patterning Technology", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD) 2008

l  Jae-Seok Yang and A. Neureuther. Crosstalk Noise Variation Assessment and Analysis for the Worst Process Corner . In Proc. Int. Symp. on Quality Electronic Design, March 2008.

l  Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Elimination of false aggressors using the functional relationship for full-chip crosstalk analysis¡±, ISQED: International Symposium on Quality Electronic Design, Mar. 2003, pp.344-347.

l  Jae-Seok Yang, JuHo Kim, and SunYoung Hwang, ¡°Path Sensitization and Gate Sizing Approach to Low Power Optimization¡±, Electronics Letters, IEE, Vol. 34, No. 7, Apr. 1998, pp. 619-620.

< Publications in Korea >

l  Jeong-Yeol Kim, Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°The Critical Network based Substrate Noise Analysis Flow¡±, the Korean Conference on semiconductors, Feb. 2004.

l  Yeo-il Yun, Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Automatic Cell Generation System Using Transistor Sizing¡±, SOC design Conference, Nov. 2003.

l  Yong-Kwan Kim, Byoung-Hyun Lee, Jae-Rim Lee, Jin-Yong Lee, Jae-Seok Yang, and Jeong-Taek Kong, ¡°Cubic-SI : Coupling Aware Delay Calculator¡±, the Korean Conference on semiconductors, Feb. 2003.

l  Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°A true aggressor determination method for accurate crosstalk analysis using functional relationship¡±, SOC design Conference, Oct. 2002.

l  Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Automatic Interconnect Analysis Methodology(IntView) for the DSM Design¡±, SOC Design Conference, Nov. 2001.

l  Jae-Seok Yang, Jeong-Yeol Kim, Dong-Soo Cho, and Jeong-Taek Kong, ¡°Automatic Interconnect Analysis Methodology(IntView) for the DSM Design Environment¡±, the Korean Conference on CAD&VLSI, May. 2001.

l  Jae-Seok Yang, Sung-Jae Kim, Ju-Ho Kim, and Sun-Young Hwang, ¡°Glitch Reduction through Path Balancing for Low-power CMOS Digital Circuits¡±, Journal of KISS (A): Computer Systems and Theory, Vol. 26, No. 10, Oct. 1999, pp. 1275-1283.

l  Jae-Seok Yang, Ju-Ho Kim, and Sun-Young Hwang, ¡°Concurrent Gate Sizing and Path Sensitization for Low-Power Design of CMOS Digital Circuits¡±, Journal of KISS (A): Computer Systems and Theory, Vol. 25, No. 7, Jul. 1998, pp. 777-784.

< Internal Samsung Publications >

l  Jeong-Yeol Kim, Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°A Substrate Noise Analysis Flow in Mixed-Signal CMOS Designs¡±, Samsung CAD/CAE Conference, Nov. 2003.

l  Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Development of SI sign-off flow for full-custom design¡±, Samsung CAD/CAE Conference, Nov. 2003.

l  Yeo-il Yun, Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Automatic Cell Generation System Using Transistor Sizing¡±, Samsung CAD/CAE Conference, Nov. 2003.

l  Jeong-Yeol Kim, Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Critical Network Simulation based Substrate Noise Analysis Flow in Mixed-Signal CMOS designs¡±, Samsung semiconductor technical Conference, Oct. 2003.

l  Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Development of SI sign-off flow in memory design using CANA-TR¡±, Samsung semiconductor technical Conference, Oct. 2003.

l  Yeo-il Yun, Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Automatic Cell Generation System Utilizing Transistor Sizing¡±, Samsung semiconductor technical Conference, Oct. 2003.

l  Jeong-Yeol Kim, Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Automatic Interconnect Modeling Verifier for DSM design¡±, Samsung CAD/CAE Conference, Nov. 2002.

l  Kyung-ho Lee, Seong-Ryong Lim, Young-Hoe Cheon, Jae-Seok Yang, and Jeong-Taek Kong, ¡°Development of EZWare's Post-layout analysis and Application of Memory Circuits¡±, Samsung CAD/CAE Conference, Nov. 2002.

l  Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Development of CANA-TR to verify the crosstalk noise in post-layout simulation¡±, Samsung CAD/CAE Conference, Nov. 2002.

l  Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Development of CANA-TR to verify the crosstalk noise in post-layout simulation¡±, Samsung semiconductor technical Conference, Oct. 2002.

l  Yong-Kwan Kim, Byoung-Hyun Lee, Jae-Rim Lee, Jin-Yong Lee, Jae-Seok Yang, and Jeong-Taek Kong, ¡°Cubic-SI : Coupling Aware Delay Calculator¡±, Samsung semiconductor technical Conference, Oct. 2002.

l  Jae-Seok Yang, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°A CANA-TR development to verify the crosstalk noise in post-layout simulation¡±, Samsung semiconductor technical Conference, Oct. 2002.

l  Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°An efficient true aggressor determination method for cross-talk analysis in UDSM design¡±, Samsung semiconductor technical Conference, Oct. 2002.

l  Jae-Seok Yang, Jeong-Yeol Kim, Joon-Ho Choi, Moon-Hyun Yoo, and Jeong-Taek Kong, ¡°Automatic Interconnect Analysis Methodology(IntView) for the DSM Design¡±, Samsung semiconductor technical Conference, Oct. 2001.

l  Seuk-Whan Lee, Jae-Seok Yang, Dong-Soo Cho, and Jeong-Taek Kong, ¡°IP Characterization using static timing analysis¡±, Samsung semiconductor technical Conference, Nov. 1999.