Kun
Yuan
Education
Kun Yuan received the B.S. degree in electronic engineering and information
science from University of Science and Technology of China, Hefei, China in
2004. He is currently working towards Ph.D. degree in electrical and computer engineering at the University of Texas, Austin.
Design of Manufacturability, Mathematical Optimization and Parallel Computing
NVIDIA Santa Clara, CA Summer 2009
Worked on RAM placement problem, and investigated on parallel acceleration using NVIDIA CUDA interface and GPU architecture .
TeraRoute Austin, TX Summer 2007
Worked on digital circuit route and physical verification for deep submicron design. Implemented DFM aware rule checking and fixing algorithms.
2nd Place (3D) and 3rd Place (2D) in Global Routing Programming Contest, ISPD, 2007
MCD Fellowship, University of Texas at Austin, 2006-2008
The Outstanding Student Scholarship, University of Science and Technology of China, 2000-2004
Journal
Kun Yuan, Jae-Seok Yang and David Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), To appear.
Minsik Cho, Kun Yuan, Yong-Chan Ban, and David Z. Pan, "ELIAD: Efficient Lithography Aware Detailed Routed with Compact PostOPC Printability Prediction", IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 7, July 2009.
Minsik Cho, Katrina Lu, Kun Yuan, and David Z. Pan, "BoxRouter 2.0: A Hybrid and Robust Global Router with Layer Assignment for Routability", ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 14 Issue 2, March 2009.
Conference
Jae-Seok Yang, Katrina Lu, Minsik Cho, Kun Yuan, and David. Z Pan, "A Multi-Objective Min-Cut Based Layout Decomposition Framework for Double Patterning Lithography", Asia and South Pacific Design Automation Conference, Jan, 2010.
David Z. Pan, Jae-Seok Yang, Kun Yuan, Minsik Cho and Yong-Chan Ban, "Layout Optimization for Double Patterning Lithography", The IEEE 8th International Conference on ASIC, Oct. 2009. (Invited)
Kun Yuan, Katrina Lu and David Z. Pan, "Double Patterning Friendly Detailed Routing with Redundant Via Consideration", Design Automation Conference (DAC), July 2009.
Kun Yuan, Jae-Seok Yang and David Z. Pan, "Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization", International Symposium on Physical Design (ISPD), March 2009.
David Z. Pan, Minsik Cho, Kun Yuan and Yong-Chan Ban, "Lithography Friendly Routing: From Construct-by-Correction to Correct-by-Construction", The 9th International Conference on Solid-State and Integrated-Circuit Technology(ICSICT)", Beijing, Oct. 2008. (Invited).
Minsik Cho, Kun Yuan, Yong-Chan Ban, and David Z. Pan, "ELIAD: Efficient Lithography Aware Detailed Routed with Compact PostOPC Printability Prediction", Proc. ACM/IEEE Design Automation Conference(DAC), June 2008.
Minsik Cho, Katrina Lu, Kun Yuan and David Z. Pan, "BoxRouter 2.0: Architecture and Implementation of a Hybrid and Robust Global Router", Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2007.
Selected Courses
Engineering Programming Language, VLSI I, Physical Design Automation, VLSI CAD Optimization, Logic Synthesis, VLSI testing, Circuit Simulation, Dependant Computing.
Skills
C++, Perl, Latex, Cadence Encounter, Mentor Calibre, Synopsys Primetime, Synopsys Design Compiler, Matlab
kyuan AT cerc DOT utexas DOT edu