Ye Wang

PhD Candidate, Dept. of Electrical and Computer Engineering, the University of Texas at Austin, [resume]

Advisor : Constantine Caramanis and Michael Orshansky

I will join the Voltus team at Cadence Austin, as a lead software engineer, under the supervision of Xiaoping Hu and Ben Gu, starting from May 20, 2018.

  • Email : 'lhy’ + (lastname) @ utexas.edu

Education

  • Ph.D, ECE, The University of Texas at Austin, Dec 2014 - Present

    • Thesis:

    • Courses: Large-Scale Optimization, Nanometer Scale IC Design, VLSI II, Combinatorics & Graph Theory, Numerical Analysis: Linear Algebra, Engineering Programming Language, Advanced Algorithm, Probability & Stochastic Process I, Advanced Probability, High Speed Arithmetic, Mixed-Signal System Design & Modeling, Data Converters, Analog IC Design

  • M.S., EE, The University of Texas at Austin, Aug. 2012 - Dec. 2014

  • B.S., EE, Zhejiang University, China, Aug. 2008 - Jun. 2012

Publications

  1. Ye Wang and Michael Orshansky, “Helper Data Reduction in SRAM PUFs via Lossy Compression”, in DATE, 2018.

  2. Aydin Aysu, Ye Wang, Patrick Schaumont, and Michael Orshansky. “A New Maskless Debiasing Method for Lightweight Physical Unclonable Functions”, in HOST, 2017.

  3. Ye Wang, Constantine Caramanis, and Michael Orshansky “Exploiting Randomness in Sketching for Efficient Hardware Implementation of Machine Learning Applications”, in ICCAD, 2016.

  4. Meng Li, Ye Wang, and Michael Orshansky “A Monte Carlo Simulation Flow for SEU Analysis of Sequential Circuits”, in DAC, 2016.

  5. Ye Wang, Constantine Caramanis and Michael Orshansky “PolyGP:Improving GP-Based Analog Optimization through Accurate High-Order Monomials and Semidefinite Relaxation”, in DATE, 2016.

  6. Ye Wang, Meng Li, Xinyang Yi, Zhao Song, Michael Orshansky and Constantine Caramanis, “Novel Power Grid Reduction Method Based on L1 Regularization”, in DAC, 2015. (slides, poster)

  7. Ye Wang, Michael Orshansky and Constantine Caramanis, “Enabling Efficient Analog Synthesis by Coupling Sparse Regression and Polynomial Optimization”, in DAC, 2014. (slides, poster)

Experience

  • Intern at Cadence Design System, Austin, TX, Jan. 2018 - May. 2018

  • Summer intern at Samsung Austin Research Center (SARC), Austin, TX, May. 2014 - Aug. 2014

  • Summer intern at Broadcom, Santa Clara, CA, May. 2013 - Aug. 2013

  • Teaching Assistant at ECE Dept, University of Texas at Austin

    • EE362K Introduction to Automatic Control, Spring 2015

    • EE381V Nanometer-scale IC Design, Fall 2014

    • EE438 Electronic Circuits, Fall 2012 & Spring 2013