Interests

VLSI systems design and Test, Parametric Tesiting, Timing verification, Effects of process variations.

Educational Background

Masters Thesis

The research was directed towards obtaining a quantitative method to measure system robustness. Geometric modeling was employed to analyze system performance and robustness was measured using surface curvature in addition to the slope.

Publications

R.Tayade, G. Choi, Fast Simulation Technique for LDPC code Analysis’ ,Pervasive Computing Conference, Las Vegas, NV, June 2004

Projects

1. Second-order Delay computation of general RC networks using Weibull Distribution approximation of the step response.
2. Implementation of serial and parallel LDPC decoder architectures on Xilinx Virtex II FPGA.
3. VLSI implementation of a LDPC decoder system using Verilog, Cadence Virtuoso and Silicon Ensemble.
4. Term paper on testing techniques for reconfigurable FPGAs.
5. Study of various BIST approaches for single stuck-at faults in combinational logic circuits.
6. VLSI implementation of FIR filter involving timing analysis and layout design using Cadence Virtuoso.
7. DLX processor simulation using Verilog HDL.
8. ISA prototype card design using ABEL HDL and Lattice CPLD.
9. Implemented Routing (Maze runner and Channel routing) and Placement (Simulated Annealing) algorithms optimized for minimum cost solutions.
10. Simulation of BCH encoder and decoder using MATLAB.
11. Design and implementation of CDMA reverse link (IS 95) using TMS 320C6201 DSP.
12. Implementation of soft & hard-decision decoders for Convolutional Codes based on Viterbi Algorithm using MATLAB.
13. Performance Analysis of receiver schemes (BPSK, BFSK, DPSK) using MATLAB.
14. Implementation of Monte-Carlo methods for solving Poissons equation using MATLAB.
15. Implementation of Chat client-server application based on TCP/IP using C.

Computer Skills

Programming Languages: C, C++, JAVA, Visual Basic, Assembly (Intel 8085,TMS 3206701/6201 DSP)
HDL Languages : Verilog, VHDL, ABEL
Scripting Languages : Tcl/Tk, VBScript, Unix shell script
Operating Systems: MS Windows ,Unix
Development Software Visual Studio (VB), Code Composer Studio, Xilinx ISE, Labview
Database Systems: Oracle, MS Access, IMS
Mathematical Tools: MATLAB v5.x, Mathematica
Simulation Software: Cadence Virtuoso, NS2, Silicon Ensemble

Work Experience

1) Summer Intern IBM Austin Research Lab. May 17- Aug’ 27
Developed a command-interpreter for a Multi-value cycle simulator for logic design using Tcl and C.
Implemented the test-infrastructure for running scan-tests using Tcl/Tk and C. The process included discovering the scan-chains (for BIST) from the VHDL design and providing an interactive interface to the user for verifying the design via both simulations and hardware tests.
2) Organization: College Of Architecture, Texas A&M University
Designation: Graduate Assistant
Duration: Aug 2000 -May 2004 ·
Responsibilties: Have been the primary web-application programmer for more than 3 years for the College of Architecture. Responsibilities include requirement analysis, design and implementation of various web-based applications. Primarily been using ASP with SQL server or MS Access. Developed several web-based systems such as online event scheduling, online course submission and grading, calendar of events, online resume builder and more.

3) Organization: Tata Infotech Ltd., Pune.
Designation: Assistant Systems Analyst.
Duration: Aug 1999 - July 2000
Responsibilities Code Development, Documentation, Database Design

• Database migration from hierarchical to relational model.
• Implementation and test of payroll system for the Govt. of India Defense services.
• Design and implementation of employee training system for TIL training division.

3) Organization: Parametric Technologies., Pune.
Designation: Project Intern.
Duration: May 1999 - July 1999
Responsibilities Developed an Image Processing software using jdk1.1.5. which implemented spatial transformations.

Certification

Sun Certified Java Programmer, May 2000.

Work Authorization

Status Eligible for practical training (F1)