l Manufacturability Aware Physical Synthesis: Seminal works on DFM were done where three major manufacturability issues were addressed during physical synthesis in novel manners, namely CMP, random defects, and lithography/printability. These are key works which constitute to synergistic DFM flow.
n Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "Wire Density Driven Global Routing for CMP Variation and Timing", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November, 2006
n Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Router with Yield-driven Wire Planning", Proc. ACM/IEEE Design Automation Conference (DAC), June, 2007
n David Z. Pan and Minsik Cho, "Synergistic Physical Synthesis for Manufacturability and Variability in 45nm Designs and Beyond", Proc. ACM/IEEE Asian and South Pacific Design Automation Conference (ASPDAC), January, 2008 (Invited)
n Minsik Cho, Hua Xiang, Ruchir Puri, and David Z. Pan, "TROY: Track Routing and Optimization for Yield", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), accepted for publication
n Tung-Chieh Chen, Minsik Cho, David Z. Pan, and Yao-Wen Chang, "Metal-Density Driven Placement for CMP Variation and Routability", Proc. ACM Int'l Symposium on Physical Design (ISPD), April, 2008
n Minsik Cho, Kun Yuan, Yongchan Ban and David Z. Pan, [exact title is not shown for blind review] A paper on lithography aware routing," submitted to Proc. ACM/IEEE Design Automation Conference (DAC), 2008
n David Z. Pan, Peng You, Minsik Cho, Anand Ramalingam, Kiwoon Kim, Anand Rajaram, and Sean X. Shi, "Nanometer IC Design and Process Integration: A Survey", The Journal of Process Control (JPC), under minor revision
n Minsik Cho, Joydeep Mitra, and David Z. Pan, "Manufacturability Aware Routing", in The Handbook of Algorithms for VLSI Physical Design Automation, CRC Press, (edited by Dr. Charles J. Alpert, Prof. Dinesh P. Mehta, and Prof. Sachin S. Sapatnekar) (Invited)
l Reliability Aware VLSI Physical Synthesis: Novel techniques for reliable VLSI physical synthesis against temperature variation and substrate noise were researched. The first work on temperature aware clock synthesis to minimize thermally induced clock skew was proposed. A high fidelity yet fast graph theoretical substrate noise model was developed and applied to guide an ultra fast substrate noise aware floorplanning for mixed-signal SOCs, which received Best Paper Nomination in ASPDAC'06.
n Minsik Cho, Suhail Ahmed, and David Z. Pan, "TACO: Temperature Aware Clock-tree Optimization", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November, 2005
n Minsik Cho, Hongjoong Shin, and David Z. Pan, "Fast Susbstrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs", Proc. ACM/IEEE Asian and South Pacific Design Automation Conference (ASPDAC), January, 2006 (Nominated for Best Paper Award)
n Minsik Cho and David Z. Pan, "Fast Susbstrate Noise-Aware Floorplanning with Preference Directed Graph for Mixed-Signal SOCs", IEEE Transactions on Very Large Scale Integratin Systems (TVLSI), accepted for publication
l High Performance Global Routing: A new global routing algorithm, BoxRouter pushed the state-of-the-art significantly, and sparked many following research works opening the global routing research renaissance (more than eight follow-up papers within one year after C4). BoxRouter received Best Paper Nomination in DAC'06, ACM/SIGDA Awards in ISPD'07, IEEE/CEDA Award, and helped me receive SRC Inventor Recognition Award.
n Minsik Cho and David Z. Pan, "BoxRouter: A New Global Router Based on Box Expansion and Progressive ILP", Proc. ACM/IEEE Design Automation Conference (DAC), July, 2006 (Nominated for Best Paper Award) [BoxRouter Download]
n Minsik Cho, Katrina Lu, Kun Yuan, and David Z. Pan, "BoxRouter 2.0: Architecture and Implementation of a Hybrid and Robust Global Router", Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November, 2007 [BoxRouter 2.0 Download]
n Minsik Cho, Katrina Lu, Kun Yuan, and David Z. Pan, " BoxRouter 2.0: A Hybrid and Robust Global Router with Layer Assignment for Routability", ACM Transactions on Design Automation of Electronic Systems (TODAES), submitted for review
l Parallel Physical Synthesis on Many/Multi-Core Architecture: The first work on parallel physical synthesis methodology to cope with the recent advancements in multi/many-core computing platforms was researched, mainly focusing on physical partitioning, a key to successful CAD parallelization.
n Minsik Cho, James D. Ma, Anthony D. Drumm, Louise H. Trevillyan, Hua Xiang, and Ruchir Puri, [exact title is not shown for blind review] A paper on parallel design closure," submitted to Proc. ACM/IEEE Design Automation Conference (DAC), 2008
l Digital Microfluidic Biochip Chip Design Automation: An efficient digital microfluidic biochip synthesis algorithm was researched to improve the completion of droplet routing. The proposed approach significantly outperformed the start-of-the-art.
n Minsik Cho and David Z. Pan, "A High Performance Droplet Router for Digital Microfluidic Biochips", Proc. ACM Int'l Symposium on Physical Design (ISPD), April, 2008
n Minsik Cho and David Z. Pan, "A High Performance Droplet Routing Algorithm for Digital Microfluidic Biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), submitted for review
l Scan Optimization in VLSI Testing: First temperature aware scan chain optimization to minimize the peak temperature of circuit-under-test (CUT) was proposed. This was also the first work to show that low power testing does not necessarily constitute lower peak temperature due to heat dissipation.
n Minsik Cho and David Z. Pan, "PEAKASO: Peak-Temperature Aware Scan-Vector Optimization", Proc. IEEE VLSI Test Symposium (VTS), April, 2006