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7

Simulator Theory of Operation

Introduction

The SPW Simulation Program Builder simulator is a fast, cycle-based signal flow simulator that can be used to model the effects of various types of signal processing systems.

The exercises in this chapter demonstrate the operation of the simulator. You start by building and simulating some simple single-rate systems. Later in the chapter, you build and simulate more complicated systems, including static multirate systems.

Single-Rate Simulation

Most blocks in the SPW block libraries are single-rate blocks. A single-rate block accepts data samples at its inputs and produces data samples at its outputs at the same rate. A system built entirely of single-rate blocks is called a single-rate system, and a simulation of such a system is called a single-rate simulation.

In this section of the tutorial, you build and simulate two single-rate systems, called "linear" and "feedback."

Linear Example

The "linear" example performs a simple linear calculation. The simulator output is a linear function of the simulator input.

Build the System

  1. Open a new BDE design window.
  2. Add one each of the following blocks:

    3. >Blocks>Signal Gen/Store>Signal Sources>Data

    >Blocks>Math>Basic>Gain

    >Blocks>Math>Basic>Add

    >Blocks>Math>Basic>Constant

    >Blocks>Signal Gen/Store>Signal Sink>Data

  3. Arrange and connect the blocks as shown in Figure 7-1.
Figure 7-1  Linear System Example

  1. Set the block parameters as follows:

    2. Source block Library/File parameter: 'yourlib/in'

    Gain block's Value parameter: 2.0

    Source block Library/File parameter: 'yourlib/out'

  2. Double-click on the Sink block and set the GET_SIM Signal Display Order parameter to 2.
  3. Close the context window.
  4. Execute the following command: 
    5. File-Save As
  5. In the dialog box, specify the logical file name "yourlib/linear.system" and then click on the OK button.

When you run a simulation of this system, the simulator generates a sequence of data values taken from the Signal Source file, multiplies each value by 2.0, adds the result together with the constant value 1.0, and writes the final sequence of resulting values to the Signal Sink file. In other words, the simulator calculates the output as a function of the input as follows:

out(i) = 2*[in(i)] + 1 i=0,1,2,3...

The simulator operates like the following C-like program code:

Create the Input Signal

  1. Open SigCalc if you have not already done so.
  2. In the SigCalc window, click on the Gen-Sine icon, which is the button with a sine wave.
  3. In the Generate Sine Wave dialog box, set the sine wave characteristics as follows:
    • Amplitude: 1
    • Frequency: 10
    • Phase in Degrees: 0.0
    • Number of Points: 100
    • Sampling Frequency: 1000
  4. Click on the OK button.

    5. SigCalc generates and displays the sine wave.

  5. Select the new sine wave signal.
  6. Execute the following command: 
    7. File-Save As
  7. In the dialog box, specify the signal file name "yourlib/in" and then click on the OK button.

Run the Simulation

  1. In the BDE design window containing the "linear" block diagram, execute the following command: 
    2. Tools-Simulation Manager
  2. In the Simulation Manager window, enter 100 into the Number of Samples field.
  3. Verify that the Simulation Manager fields and options are set as follows:
    • Design: yourlib/linear.system
    • Configuration: config/bde.default
    • Engine: SPB-I
    • Create and Run buttons on
    • Debug button off
    • Samples: 100
    • Noise Seed: 1
  4. In the Simulation Manager window, execute the following command:
    5. File-Save As
  5. In the File Save As dialog box, verify that the toolrun name is yourlib/linear.toolrun, and then click on the OK button.
  6. Click on the Start button.
  7. Allow the simulation to run to completion.

View the Results

  1. In the Tool Launch area of the Simulation Manager window, click on the SigCalc button.
  2. In the simulation Files Preview dialog box, click on the OK button.

    3. SigCalc displays the simulation input signal and output signal.

  3. Set the Win Size to 100.
  4. Execute the following command: 
    5. Customize-Signal Properties
  5. In the Customize Signal Properties dialog box, change the Point Style option button to Single Point.
  6. Click on the OK button.

    7. SigCalc displays the signals as shown in Figure 7-2. The Single Point display mode emphasizes the discrete nature of the signal data.

Figure 7-2  Linear Simulation Results

Block Scheduling

The simulator must "schedule" the blocks in the system before it can run the simulation. In other words, it must determine the block execution sequence so that for each block, the input data is available for calculating the output data.

Here is one possible schedule:

  1. The Constant block produces a data sample with the value 1.0.
  2. The Signal Source block reads one data sample from the input file.
  3. The Gain block multiplies the signal value by 2.0.
  4. The Adder block adds the output of Gain block with the output of the Constant block (2.0*in+1.0).
  5. The Signal Sink block writes this result to the output file.

There is more than one valid schedule. For example, Step 1 could be done after Step 2 or after Step 3 rather than at the beginning, and the results would be the same. The actual schedule used depends on the instance numbers that BDE assigns to the blocks, which depends on the order in which the blocks were added to the design.

View the Schedule in Debug Mode

To find out the actual schedule used, do the following:

  1. In the Simulation Manager window, toggle on the Debug option.
  2. Click on the Start button.

    3. After a brief delay, the Simulation Manager displays the Interactive Simulation debugger window.

  3. Wait for the prompt (>) to appear in the Interactive Simulation Commands window of the debugger.
  4. Click on the Step button repeatedly.

    5. The simulator successively highlights the blocks in the block diagram, showing the order in which the blocks are executed. The simulator repeats the same block sequence for each simulation iteration.

  5. In the Interactive Simulation debugger window, execute the following command: 
    6. File-Exit

Single-Rate Simulation

The Linear system is an example of a single-rate model. When the program code is executed for a block, each input port consumes one sample, and each output port produces one sample. All blocks in the system operate at the same rate, and each block performs signal processing exactly once per program iteration. Execution of the simulation is very fast because the blocks are statically scheduled.

Simulator Principles

The simulator operates in an iterative loop. In each execution of the loop, the simulator determines all the signal values throughout the system. There are no signal-processing delays associated with any blocks used in this system. Therefore, each iteration is completely independent of any other iteration.

The simulator does not consider the sampling frequency of the system. It simply processes signal data one data sample at a time. The sampling frequency of the signal source (1000 in this case) is like a "comment" attached to the signal file, which has no effect on the simulation results.

Feedback Example

The "Feedback" example shows how the simulator handles a feedback loop in a system design. A feedback loop is a series of connections that feed a block output signal back to an input of the same block. Thus, the output of a block in a feedback loop affects the signal values appearing at its own input.

Some feedback loops are illegal. For example, you generally cannot connect a block output directly to the same block's input, as shown in Figure 7-3. If you do this, the simulator reports an error because it cannot calculate the output value without knowing the input value. In other words, the simulator cannot generate a valid schedule for the simulation program.

Figure 7-3  Illegal Feedback Loop

In order to work, a feedback loop must contain at least one block with a delay, as the Feedback example demonstrates.

Build the System

  1. In the BDE design window, delete the Gain block and Constant block.
  2. Add one instance of the following block:

    3. >Blocks>Memory/Delay>Unit Delay

  3. Arrange and connect the blocks as shown in Figure 7-4.
Figure 7-4  Completed Feedback System Block Diagram

  1. Execute the following command: 
    2. File-Save As
  2. In the dialog box, specify the logical file name "yourlib/feedback.system" and then click on the OK button.

The Unit Delay block passes the value on its input "in" to its output "out" after a delay of one simulation iteration (one data sample). The output on the very first simulation iteration is determined by a block parameter setting, which is 0.0 by default.

The simulator calculates its output as a function of its input and its previous output as follows:

out(0) = in(0)

out(i) = in(i) + out(i-1) i=1,2,3...

The simulator operates like the following C-like program code:

Run the Simulation

  1. In the Simulation Manager window, change the design name specified in the Design field from yourlib/linear.system to yourlib/feedback.system.
  2. Verify that the Simulation Manager fields and options are set as follows:
    • Design: yourlib/feedback.system
    • Configuration: config/bde.default
    • Engine: SPB-I
    • Create and Run buttons on
    • Debug button off
    • Number of Samples: 100
    • Noise Seed: 1
  3. In the Simulation Manager window, execute the following command:
    4. File-Save As
  4. In the File Save As dialog box, enter the name yourlib/feedback.toolrun, and then click on the OK button.
  5. Click on the Start button.
  6. Allow the simulation to run to completion.

View the Results

  1. In the Simulation Manager window, click on the SigCalc button.
  2. In the simulation Files Preview dialog box, click on the OK button.

    3. SigCalc displays the simulation input signal and output signal as shown in Figure 7-5.

  3. After you view the signals, turn the SigCalc window into an icon.
Figure 7-5  Feedback Simulation Results

State Variable

The internal programming code of the Unit Delay block contains a "state variable," which carries information from one iteration to the next. The state variable contains information about the current state of the block. In effect, the Unit Delay block operates like two separate blocks: a Run Input block and a Run Output block. On each iteration, the Unit Delay block transfers the value of the state variable to the output and later sets the state variable equal to the input value.

Block Scheduling

Here is one possible schedule for the feedback system:

  1. The Run Output section of the Unit Delay block generates a data sample equal to the previous input sample received at the block (or 0.0 initially).
  2. The Signal Source block reads one data sample from the input file.
  3. The Adder block adds the output of the Source block with the output of the Unit Delay block, producing a data sample on its output.
  4. The Run Input section of the Unit Delay block stores the value on its input into its internal state variable (to be used in the next program iteration).
  5. The Signal Sink block writes this result to the output file.

View Schedule in Debug Mode

To find out the actual schedule used, do the following:

  1. In the Simulation Manager window, toggle on the Debug option.
  2. Click on the Start button.

    3. After a brief delay, the Simulation Manager displays the Interactive Simulation debugger window.

  3. Wait for the prompt (>) to appear in the Interactive Simulation Commands window of the debugger.
  4. Click on the Step button repeatedly.

    5. The simulator successively highlights the blocks in the block diagram, showing the order in which the blocks are executed. The simulator repeats the same block sequence for each simulation iteration. The Unit Delay block is highlighted twice in this schedule because its Run Output and Run Input sections are executed at different times in the schedule.

  5. In the Interactive Simulation debugger window, execute the following command: 
    6. File-Exit
  6. In the Simulation Manager window, execute the following command: 
    7. File-Exit

Static Multirate Simulation

For some types of systems, you might want different parts of the system to operate at different sampling frequencies. For example, a system might contain two parts: one for processing the individual components of a two-component vector signal and another part for performing further signal processing directly on the vector signal. It might be desirable to make the first part operate at 1000 Hz while the second part operates at 500 Hz.

For systems such as these, you can create a "static multirate" system that uses different, specified sampling frequencies for different parts of the system. A transition from one sampling frequency to another in the system design is carried out by using a static multirate block.

Single-Rate Simulation

In a single-rate system such as the Linear and Feedback examples, the simulator uses a fixed sampling frequency (iteration rate) to simulate the entire system. The simulator calculates the value of every signal in the system at every iteration, and all blocks in the system perform signal processing at this same rate.

In a single-rate simulation, the simulator creates a program containing a single loop, which corresponds to one iteration. In each pass through the program loop, each block in the system performs signal processing once.

Multirate Simulation

In a static multirate simulation, the simulator creates a program containing a series of nested loops, each loop corresponding to a section of the system operating at a particular sampling frequency. Different parts of the system are simulated at different rates. The sampling frequency corresponding to the outermost loop is equal to the largest common factor of the various sampling frequencies used throughout the system.

For example, consider a static multirate system containing two sections, one operating at 60 Hz and the other at 8000 Hz. The frequency corresponding to the outermost program loop is 20 Hz because 20 is the largest number that divides evenly into both 60 and 8000. Inside the outermost loop are two smaller loops: one that is executed 3 times (corresponding to 60 Hz) and another smaller loop that is executed 400 times (corresponding to 8000 Hz).

The simulation program does not consider the actual frequencies used in the system; it merely sets up the ratios corresponding to different simulation rates and processes the signal data in the proper sequence. The ratios are determined by the types of static multirate blocks used and their parameter settings.

Multirate Blocks

The inputs and outputs of a static multirate block operate at different sampling frequencies. The sampling frequency ratio between the input side and the output side of the block depends on the type of block and the block parameter settings. For example, a block that combines two sequential scalar values into a two-component vector can simulate operation at 1000 Hz at its scalar input and 500 Hz at its vector output.

In general, there are two kinds of multirate blocks, "static" and "dynamic." A static multirate block has a fixed relationship between the operating rates of the inputs and the outputs, such as a 2-to-1 sampling frequency ratio in the scalar-to-vector example just described. In a dynamic multirate block, the ratio between the input and output rates can change during the course of a simulation. Dynamic multirate blocks are covered in Chapter 9, "Working with Dynamic Multirate."

Base Rate

In any system, one block instance in the design can be designated the "base" block instance. The sampling frequency for one output pin of the base block is specified explicitly by the system designer. The assigned sampling frequency is called the "Base Rate." All other sampling frequencies throughout the static multirate system are referenced to the Base Rate. Sampling relationships between different parts of the system are established by the static multirate blocks used in the system.

Create Another Library

For the following exercises, you create a large number of signals. You might want to create a separate library just to contain these signals.

To create a new library, do the following:

  1. In the File Manager window, execute the command: 
    2. Libraries-Setup
  2. With the Create New Library option toggled on, click on the Next>> button.
  3. With the Create Unmanaged Library button toggled on, click on the Next>> button.
  4. In the Library Name field, enter a name for your library. For example, if your name is Joe, you could enter the name "joesigs". In the text of the tutorial manual, the name yoursigs is used to represent the name of your library for storing signals.
  5. In the Path to Library field, enter the directory path in which to create the library.
  6. Click on the OK button.

Downsampling

In the downsampling exercise, you reduce the sampling frequency of a signal in various ways and examine the results.

Build the System

  1. In a new BDE window, build the system shown in Figure 7-6. Use the following blocks:

    2. >Blocks>Signal Gen/Store>Signal Sources>Data

    >Blocks>Multirate>Resample>Downsample

    >Blocks>Multirate>Resample>Decimate

    >Blocks>Filter>Misc. Filters>Low Pass

    >Blocks>Signal Gen/Store>Signal Sink>Data

Figure 7-6  Downsampling Test System

  1. Set the multirate downsampling factor to 2 in both Down Sample blocks and in the Decimate block, as shown in Figure 7-6. The parameter for each block is inside the block symbol.
  2. Set the Library/File name parameters of the Source and Sink blocks as follows:
    • Source block: 'test_lib/mary'
    • top Sink block: 'yoursigs/down2'
    • middle Sink block: 'yoursigs/down2f'
    • bottom Sink block: 'yoursigs/dec2'
  3. Double-click on each Source and Sink block and set the GET_SIM Signal Display Order parameters to the values shown in the figure.
  4. Double-click on the Lowpass Filter block and set the Sampling Frequency parameter to 8000.0 and the Cutoff Frequency parameter to 4000.0.
  5. Select the output of the Source block by selecting the junction dot (looks like a diamond) between the Signal Source and Down Sample blocks. Execute the Design-Multirate Edit command.
  6. In the dialog box, set the Base Rate to 8000.0 and then click on the OK button.
  7. Use the File-Save As command to save the system under the logical file name yourlib/mr1.system. Substitute your own library name for yourlib.

Simulate the System

  1. Execute the following command:
    2. Tools-Simulation Manager
  2. In the Simulation Manager window, set the Number of Samples field to 40000.
  3. In the Simulation Manager window, execute the following command:
    4. File-Save As
  4. In the File Save As dialog box, verify that the toolrun name is yourlib/mr1.toolrun, and then click on the OK button.
  5. Click on the Start button.
  6. When the simulation is done, click on the SigCalc button.
  7. In the simulation Files Preview dialog box, click on the OK button.
  8. Close the Simulation Manager window.
  9. If the calculator is present in the SigCalc window, remove it by clicking on the Calc button.
  10. Set the SigCalc window to Time Align mode, if it is not already in that mode, by selecting a signal and then clicking on the Point Align button.
  11. Select a short range of data points and execute the following command: 
    12. View-Selected Range 
 
    
Your view might resemble the one shown in Figure 7-7.

Note: In the figure, the "point style" is set to "Single Point" (an option in the Customize-Signal Properties command).

Figure 7-7  Downsampling Simulation Results

Interpreting the Results

The Time Align mode displays signals on a common time base, so the horizontal spacing between data points depends on the sampling frequency.

The Source block provides a signal at 8 kHz. You specify this rate for the simulator by using the Design-Multirate Edit command. The simulator keeps track of all the sampling frequencies throughout the system relative to the Base Rate.

The Down Sample block allows every other data sample to pass through and discards the data samples in between. Therefore, the output operates at 4 kHz, which is half the rate of the input. The Signal Sink block connected to the Down Sample block output records the sampling frequency along with the data samples.

The Lowpass Filter block, which has been set to operate at 8 kHz, filters the original signal using a cutoff frequency of 4 kHz. The filter removes the higher frequency components of the signal and also causes a delay from input to output of 4.5 samples at 8 kHz. (The amount of delay is calculated as (n-1)/2 samples, where n is the number of filter coefficients.) This Filter block is a single-rate block, so both the input and output operate at 8 kHz. The Down Sample block connected to the output reduces the operating rate to 4 kHz.

The Decimate block performs both lowpass filtering and downsampling. It operates like a combination of a Lowpass block and a Down Sample block. Lowpass filtering prevents aliasing, which can otherwise occur with downsampling alone. The cutoff frequency of the built-in lowpass filter is automatically set to one-half the output sampling frequency of the Decimate block, 4 kHz in this case. Again, filtering causes a delay from input to output. The resulting output signal resembles the input signal with respect to time, except for the reduction in sampling frequency and a delay of 12 samples at 4 kHz.

Upsampling

In the upsampling exercise, you increase the sampling frequency of a signal in various ways and examine the results.

Build the System

  1. In a new BDE window, build the system shown in Figure 7-8. Use the following blocks:

    2. >Blocks>Signal Gen/Store>Signal Sources>Data

    >Blocks>Multirate>Resample>Upsample

    >Blocks>Multirate>Resample>Repeat

    >Blocks>Multirate>Resample>Interpolate

    >Blocks>Signal Gen/Store>Signal Sink>Data

Figure 7-8  Upsampling Test System

  1. Set the multirate upsampling factor to 3 in the Up Sample, Repeat, and Interpolate blocks, as shown in Figure 7-8.
  2. Set the Library/File name parameters of the Source and Sink blocks as follows:
    • Source block: 'test_lib/mary'
    • top Sink block: 'yoursigs/up3'
    • middle Sink block: 'yoursigs/repeat3'
    • bottom Sink block: 'yoursigs/interp3'
  3. Double-click on each Source and Sink block and set the GET_SIM Signal Display Order parameters to the values shown in the figure.
  4. Select the output of the Source block by selecting the junction dot (looks like a diamond) between the Signal Source and the Up Sample blocks.
  5. Execute the Design-Multirate Edit command.
  6. In the dialog box, set the Base Rate to 8000.0 and then click on the OK button.
  7. Use the File-Save As command to save the system under the logical file name yourlib/mr2.system. Substitute your own library name for yourlib.

Simulate the System

  1. Execute the following command:
    2. Tools-Simulation Manager
  2. In the Simulation Manager window, set the Number of Samples field to 40000.
  3. In the Simulation Manager window, execute the following command:
    4. File-Save As
  4. In the File Save As dialog box, verify that the toolrun name is yourlib/mr2.toolrun, and then click on the OK button.
  5. Click on the Start button.
  6. When the simulation is done, click on the SigCalc button.
  7. In the simulation Files Preview dialog box, click on the OK button.
  8. With SigCalc in Time Align mode, examine a short range of data points in the signals, as shown in Figure 7-9.

Note: In the figure, the "point style" is set to "Single Point" (with the Customize-Signal Properties command)

Figure 7-9  Upsampling Simulation Results

Interpreting the Results

The Source block provides a signal at 8 kHz. The Up Sample block inserts two zero-valued data points between adjacent data points received at the input to produce the output. Therefore, the output operates at 24 kHz, or three times faster than the input.

Similarly, the Repeat block repeats each incoming sample three times to produce the output. The output also operates at 24 kHz, or three times faster than the input.

The Interpolate block performs upsampling followed by lowpass filtering. This eliminates unwanted images of the spectrum, which can otherwise occur with upsampling alone. The cutoff frequency of the lowpass filter is automatically set to one-half the input sampling frequency of the Interpolate block, or 4 kHz in this case. Filtering causes a delay from input to output. The resulting output signal resembles the input signal with respect to time, except for the increase in sampling frequency and the delay.

Downsampling and Upsampling

In the following exercise, you perform both downsampling and upsampling in the same system.

Build the System

Build the system shown in Figure 7-10 by combining the blocks from the previous two exercises (yourlib/mr1.system and yourlib/mr2.system). This is the procedure:

  1. Use the Edit-Copy command to copy all of the blocks and connections from the yourlib/mr2.system model (except for the Source block).
  2. Use the Edit-Paste command to paste the blocks and connections into the yourlib/mr1.system model.
  3. Connect the blocks together with wires as shown in 7-10.
Figure 7-10  Downsampling and Upsampling Test System

  1. Double-click on each Source and Sink block and set the GET_SIM Signal Display Order parameters to the values shown in Figure 7-10.
  2. Use the File-Save As command to save the system under the logical file name yourlib/mr3.system. Substitute your own library name for yourlib.

Simulate the System

  1. Execute the following command:
    2. Tools-Simulation Manager
  2. In the Simulation Manager window, set the Number of Samples field to 40000.
  3. In the Simulation Manager window, execute the following command:
    4. File-Save As
  4. In the File Save As dialog box, verify that the toolrun name is yourlib/mr3.toolrun, and then click on the OK button.
  5. Click on the Start button.
  6. When the simulation is done, click on the SigCalc button.
  7. In the simulation Files Preview dialog box, click on the OK button.
  8. With SigCalc in Time Align mode, examine a short range of data points in the signals as shown in Figure 7-11.

Note: You can use the SigCalc in the "Time Ruler" mode, which allows all the signals to be displayed simultaneously. Use the Customize-Time Ruler-Mode Toggle command to change the display mode.

Figure 7-11  Downsampling and Upsampling Results

Interpreting the Results

There are three operating rates in the system: 4 kHz, 8 kHz, and 24 kHz. The simulator implements the simulation program as a set of nested loops. The slowest, outermost loop performs the 4 kHz signal processing, while the fastest, innermost loop performs the 24 kHz processing. The Time Align mode displays all the signals on a common time base.

Resampling

In the resampling exercise, you change the sampling frequency of a signal in various ways and examine the results.

Build the System

  1. In a new BDE window, build the system shown in Figure 7-12. Use the following blocks:

    2. >Blocks>Signal Gen/Store>Signal Sources>Data

    >Blocks>Multirate>Resample>Ratio

    >Blocks>Signal Gen/Store>Signal Sink>Data

Figure 7-12  Resampling Test System

  1. In the Resample block, set the upsampling factor to 3 and the downsampling factor to 2, as shown in Figure 7-12.
  2. Set the Library/File name parameters of the Source and Sink blocks as follows:
    • Source block: 'test_lib/mary'
    • Sink block: 'yoursigs/resamp32'
  3. Select the output of the Source block by selecting the junction dot between the Signal Source and Resample blocks.
  4. Execute the Design-Multirate Edit command.
  5. In the dialog box, set the Base Rate at that point to 8000.0.
  6. Use the File-Save As command to save the system under the logical file name yourlib/mr4.system. Substitute your own library name for yourlib.

Simulate the System

  1. Execute the following command:
    2. Tools-Simulation Manager
  2. In the Simulation Manager window, set the Number of Samples field to 40000.
  3. In the Simulation Manager window, execute the following command:
    4. File-Save As
  4. In the File Save As dialog box, verify that the toolrun name is yourlib/mr4.toolrun, and then click on the OK button.
  5. Click on the Start button.
  6. When the simulation is done, click on the SigCalc button.
  7. In the simulation Files Preview dialog box, click on the OK button.
  8. With SigCalc in Time Align mode, examine a short range of data points in the signals. Figure 7-13 shows an example.
Figure 7-13  Resampling Simulation Results

Interpreting the Results

The Resample block does upsampling by a factor of 3, lowpass filtering, and downsampling by a factor of 2. The input sampling rate is 8 kHz, and the output sampling rate is 12 kHz, a ratio of 3 to 2. The internal lowpass filter prevents aliasing and eliminates unwanted images of the spectrum. The filter cutoff frequency is automatically set to one-half the input or output sampling rate, whichever is smaller (4 kHz in this case).

There are three operating rates in the system: 8 kHz at the Resample block input, 12 kHz at the Ratio block output, and 24 kHz inside the Resample block. The simulator implements the simulation program as a set of nested loops, as in the previous example.

Conclusion

This is the end of the Simulator Theory of Operation tutorial. To prepare for the next tutorial lesson, set the Point Style back to Interpolated in SigCalc using the Customize-Signal Properties command. Then close the BDE, Simulation Manager, and SigCalc windows.

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