Tung-Yeh Wu / 吳東燁


Tung-Yeh Wu / 吳東燁
Last Update: Feb 4, 2009
Hi, welcome your visiting to my website. My name is Tung-Yeh Wu (吳東燁). In the University of Texas at Austin, I am a PhD student in Electrical and Computer Engineering (ECE) and also a member of Computer Engineering Research Center (CERC). This website could provide you not only with a few ideas about my research interest, my recent research works, and my previous research result, but also with some helpful information such as the tutorial of EDA tools and the links I often visit. Please feel free to contact me if you have any opinion or suggestion for my website.

About Me

Education

Ph.D. program in Electrical and Computer Engineering, The University of Texas at Austin Jan 2007~
M.S. in Electrical and Computer Engineering, The University of Texas at Austin Dec 2006
B.S. in Electrical Engineering, National Chung-Cheng University Jun 2002

Experience

Research Interest

Advisor

My TA Class

Useful Link

Cadence_2004 Tutorial - I use this tutorial for lab in my TA class. It goes through from schematic to post layout simulation
Hspice Tutorial - This is a tutorial for a hspice beginner
PCB Design Tutorial - It's a very good reference if it's your first time designing a PCB.
Convert power point ppt to eps - I copy this page from http://www.cs.bu.edu/~reyzin/pictips.html
Encounter Tutorial - There is a very nice Encounter tutorial for Cadence Encounter in gui from UCSD.
ANSI logic gate symbols - There is a small collection of logic gate symbols in both .svg and .png format. It's convenient if you want to draw some schematics. It is originally from http://commons.wikimedia.org/wiki/Category:ANSI_logic_gates

Contact Me