James Ban

Welcome to James' Home

Welcome to my Webpage.  I am James Ban (korean name: Yong-Chan Ban, 반용찬).  I am pursuing my PhD Degree (since August 2007) at the UT VLSI Design Automation Laboratory in Department of Electrical and Computer Engineering at the University of Texas at Austin.  My advisor is  Professor David Z Pan.  My reseach at UT is focussed on Lithography Driven Physical Design and  Design for Manufacturability (DFM).  Take a look at my Research page to know more about my research work.

From May 2002 to May 2007, I worked for Samsung Electronics as a Senior Engineer in the Semiconductor R&D Center on VLSI CAD development. In particular, I've developed in-house lithography simulator which is pursuing lithographic DFM and is based on the Cadence Virtuoso layout editor for real Litho Friendly Layout (LFL). From February 2000 to April 2002, I worked as a Research Assistant with Silicon Tech Ltd. on the development of application S/W for Photoresist coater/developer. From 1997 to January 2000, I've worked as a Research Assistant on the development of TCAD simulator; those are the low-energy ion-implantation, the plasma sheath modeling for a dry etching process and the sputtering deposition modeling. I've received two Best Paper awards at the Samsung Group Technical Conference in 2004 and 2006 and DAC Young Student Support Program Award in 2008.

In summer 2008, I worked for Freescale Semiconductor (formerly Motorola Semiconductor) at Austin for my internship. My work was a process variability aware sensitivity analysis and optimization for 45nm & 32nm standard cell design. 

This summer, I worked for GlobalFoundries (formerly AMD) at Sunnyvale, CA.

To summarize my career,
Semiconductor Process & Devices Modeling:TCAD (1997~2000) → Appl. S/W for Semiconductor Equipments (2000~2002) → PhotoLithography, OPC & RDR (2002~2007) → VLSI Layout Automation, Circuit Design & DFM (2007~ ).

Now I'm living in Austin with my wife (You-Kyoung) and my daughters (Ye-Eun and Yena).