James Ban

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Univ. of Texas, Austin
UT ECE
UT DA Lab
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puceResearch Areas

pucePublications

Conference

24.  Min-Sik Cho, Yong-Chan Ban, and David Pan, “Double Patterning Technology Friendly Detailed Routing”, Proc. IEEE/ACM Int'l Conference on Computer-Aided Design (ICCAD), November 2008.

23.  David Pan, Min-Sik Cho, Kun Yuan, Yong-Chan Ban, “Lithography Friendly Routing: From Construct-by-Correction to Correct-by-Construction”, The 9th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), June, 2008. (invited)

22.  Min-Sik Cho, Kun Yuan, Yong-Chan Ban, and David Pan, “ELIAD: Efficient Lithography Aware Detailed Router with Compact PostOPC Printability Prediction”, Proc. ACM/IEEE Design Automation Conference (DAC), June, 2008.

21.  Yong-Chan Ban, Dong-Yoon Lee, Ji-Suk Hong, Moon-Hyun Yoo, and Jeong-Taek Kong, “OPC and verification accuracy enhancement using the 2D wafer image for the low-k1 memory devices”, Intl. Symp. SPIE Microlithography 6154, 61540J, 2006.

20.  Yong-Hee Park, Yong-Chan Ban, Duck-Hyung Hur, Dong-Hyun Kim, Ji-Suk Hong, Moon-Hyun Yoo, and Jeong-Taek Kong, “Efficient OPC model generation and verification for focus variation” , Intl. Symp. SPIE Microlithography 6154, 61543B, 2006.

19. Yong-Chan Ban, Soo-Han Choi, Ki-Hung Lee, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo and Jeong-Taek Kong, “A Fast Lithography Verification Framework for Litho-Friendly Layout Design”, 6th IEEE Intl. Symp. on Quality Electronic Design (ISQED), 2005.

18.  Soo-Han Choi, Tae-Hoon Park, Eunsung Kim, Hyoung-Joo Youn, Dae-Youp Lee, Yong-Chan Ban, A-Young Je, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, and Jeong-Taek Kong , “Illumination and multi-step OPC optimization to enhance process margin of the 65nm node device exposed by dipole illumination”, Intl. Symp. SPIE Microlithography 5754, 838, 2005.

17.  Wan-Suk Cho, Yong-Chan Ban, et. al. “OPC(optical proximity correction) of F-Poly pattern”, Intl. SOC Design Conference, Nov. 2004.

16.  Ji-Suk Hong, Chul-Hong Park, Dong-Hyun Kim, Soo-Han Choi, Yong-Chan Ban, Yoo-Hyon Kim, Moon-Hyun Yoo, and Jeong-Taek Kong, “Accurate gate CD control through the full-chip area using the dual model in the model-based OPC”, Intl. Symp. SPIE Microlithography 5377, 571. 2004.

15.  Yong-Chan Ban, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo and Jeong-Taek Kong, “Optimization of Lithography Simulation Parameters using Empirical Data Sets for Low k1 D/R Requirement”, Samsung semiconductor technical Conference, Oct., 2004.

14.  Soo-Han Choi, Yong-Chan Ban, Ki-Heung Lee, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, and Jeong-Taek Kong , “Simulation-based critical-area extraction and litho-friendly layout design for low-k1 lithography”, Intl. Symp. SPIE Microlithography 5377, 713, 2004.

13.  Yong-Chan Ban, Soo-Han Choi, et. al. “Development of the lithography simulator (FAITH) and the litho-friendly layout (LFL) based on a layout editor”, Samsung CAD/CAE Conference, Nov. 2003. The excellent paper award.

12.  Soo-Han Choi, Yong-Chan Ban, Ki-Heung Lee, Dong-Hyun Kim, Ji-Suk Hong, Yoo-Hyon Kim, Moon-Hyun Yoo, and Jeong-Taek Kong, “Simulation-based optical rule checking and litho-friendly layout design for low-k1 lithography”, Samsung semiconductor technical Conference, Oct., 2003.

11.  Dong-Hyun Kim, Ji-Suk Hong, Yong-Chan Ban, et. al. “Method of CD Variation Reduction using Etch Dummy Insertion”, The 10th Korean Conference on semiconductors, Feb. 2003.

10.  Ohseob Kown, Yongchan Ban, Sukin Yoon and Taeyoung Won, “Modeling and Simulation of 3D Structures for Gigabit DRAM”, The 7th Korean Conference on Semicomductors, Korea University, Seoul, Korea, Feb. 2000.

9.    Yongchan Ban, Ohseob Kown and Taeyoung Won, “Monte Carlo Simulation of Ultra-low Energy Ion Implantation”, The 7th Korean Conference on Semiconductors, Korea University, Seoul, Korea, Feb. 2000

8.    Ohseob Kown, Yongchan Ban, Sukin Yoon and Taeyoung Won, “Modeling and Simulation of 3D Structures for Gigabit DRAM”, International Conference on Modeling and Simulation of Microsystems (MSM 2000), U.S. Grant hotel, San Diego, March 27-29 2000.

7.    Yongchan Ban, Ohseob Kown, and Taeyoung Won, “Modeling of Computationally Efficient 3-D Ultra-low Energy Ion Implantation Using Monte-Carlo Method”, International Conference on Modeling and Simulation of Microsystems (MSM 2000), U.S. Grant hotel, San Diego, March 27-29 2000.

6.    Yongchan Ban, Taeyoung Won, “3D Monte Carlo Simulation of Cu Sputtering Process”, IEEE International Region Ten Conference, Cheju, Korea, September 15-17, 1999.

5.    Yongchan Ban, Jaehee Lee and Taeyoung Won, “Modeling of Cu Sputtering Process and  Development of High Speed Simulator”, The 6th Korean Conference on Semiconductors 1999, pp489-490, Yensei University, Seoul, Korea Feb. 9-11, 1999.

4.    Yongchan Ban, Taeyoung Won, “3D Modeling of Sputter Process with Monte Carlo Method”, IEEE Simulation of Semiconductor Processes and Devices 1998 (SISPAD'98), pp. 161-164, IMEC vzw, Leuven, Belgium, September 2-4, 1998.

3.    Yongchan Ban, Jaehee Lee, Sangho Yoon, Yountae Kim, Ohseob Kwon and Taeyoung Won, “Monte Carlo Simulation of Ion in an RF Plasma etching System”, IEEK conference, Vol. 20, No. 2, pp.525-528, 1997.

2.    Sangho Yoon, Jaehee Lee, Yountae Kim, Ohseob Kwon, Yongchan Ban and Taeyoung Won, “Three-Dimensional Unstructured Delaunay Adaptive Mesh Generation and R-LOCOS Simulation”, IEEK conference, Vol. 20, No. 2, pp.529-532, 1997.

1.    Ohseob Kwon, Yongchan Ban, Jaehee Lee, Sangho Yoon, Yountae Kim and Taeyoung Won, “Development of Three-dimensional Etching Simulator for a Plasma Etching Process”, IEEK conference, Vol. 20, No. 2, pp.521-523, 1997.

 

Journals

13.  Min-Sik Cho, Yong-Chan Ban, and David Pan, “Double Patterning Technology Friendly Detailed Routing”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pending

12.  Min-Sik Cho, Kun Yuan, Yong-Chan Ban, and David Pan, “ELIAD: Efficient Lithography Aware Detailed Router with Compact PostOPC Printability Prediction”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), pending

11.   Yongchan Ban, Ohseob Kwon, and Taeyoung Won, “Monte Carlo Simulation of Ultra-low Energy Ion Implantation”, Journal of The Korean Physical Society, SCI, vol. 39, No. 1, pp. 93-99, 2001.

10.   Ohseob Kwon, Yongchan Ban, Sukin Yoon, and Taeyoung Won, “3Modeling and Simulation of 3D Structures for Gigabit DRAM”, Journal of The Korean Physical Society, SCI, vol. 39, No. 1, 2001.

9.     Yongchan Ban, Jaehee Lee, and Taeyoung Won, “Modeling of 3D Monte Carlo Ion Implantation in the Ultra-Low Energy for the Fabrication of Giga-Bit Devices”, Journal of The Korean Institute of Electronics, vol. 37-SD, pp. 753-762. 2000.

8.     Yongchan Ban, Jaehee Lee, and Taeyoung Won, “3D Calculation of Copper Sputtering Yield by Monte Carlo Method”, Journal of The Korean Physical Society, SCI, vol. 35, December, pp. S829-S833, 1999.

7.     Jaehee Lee, Ohseob Kwon, Yongchan Ban and Taeyoung Won, “Development of High Performance Massively Parallel Processing Simulator for Semiconductor Etching Process”, Journal of The Korean Institute of Electronics, vol. 36-D, pp. 865-872. 1999.

6.     Jaehee Lee, Yongchan Ban and Taeyoung Won, “Massive Parallel Processing Algorithm for Semiconductor Process Simulation”, Journal of The Korean Institute of Electronics, vol. 36-D, pp. 48-58, 1999.

5.     Ohseob Kwon, Yongchan Ban and Taeyoung Won, “Efficient Shadow-Test Algorithm for the Simulation of Dry Etching and Topographical Evolution”, Journal of The Korean Institute of Electronics, vol. 36-D, pp. 41-47, 1999.

4.     Yongchan Ban, Jaehee Lee and Taeyoung Won, “Calculation of Sputter Yield using Monte Carlo techniques”, Journal of The Korean Institute of Electronics, vol 35-D, pp. 59-67, 1998.

3.     Yountae Kim, Jaehee Lee, Sangho Yoon, Ohseob Kwon, Yongchan Ban and Taeyoung Won, “A study of the fabrication of AlGaAs/GaAs HBT with an air-bridge isolation structure induced by isotropic undercut etching”, Journal of The Korean Institute of Electronics, vol. 35-D, pp. 458-465, 1998.

2.    Yongchan Ban, Jaehee Lee, Sangho Yoon, Ohseob Kwon, Yountae Kim and Taeyoung Won, “Calculation of Ion Distributions in an RF Plasma Etching System Using Monte Carlo Methods”, Journal of The Korean Institute of Electronics, vol. 35-D pp. 472-480, 1998.

1.    Ohseob Kwon, Jaehee Lee, Sangho Yoon, Yongchan Ban, Yountae Kim and Taeyoung Won, “Modeling of Plasma Etching and Development of Three-Dimensional Topography Simulator”, Journal of The Korean Institute of Electronics, vol. 35-D, pp. 119-126, 1998.

 

Patents

4.     “Phase edge phase shift mask enforcing a width of a field gate and image fabrication method thereof” Patent No: P0064641 (Korea),  IE-200206-022-1-US0 (US)

3.     “Semiconductor Sputter Process Simulation Method Using Monte Carlo Method" Patent No: P0448083 (Korea)

2.     “Parallel Processing Method for Semiconductor Etching Process Simulation” Patent No: P0042646 (Korea)

1.     “Effective Method of 3D Ion Implantation Simulation” Patent No: P0049054 (Korea)

 

James Ban © 2008

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