Young-Il Kim

ACES 6.140 The University of Texas at Austin, Austin, TX 78712
E-mail: yikim@at cerc.dot.utexas.dot.edu

EDUCATION & ACADEMIC EXPERIENCE

University of Texas at Austin, Austin, TX

Postdoctoral Researcher, Electrical and Computer Engineering, Sep., 2007 - present $\bullet$ Advisor: Dr. Jacob A. Abraham

Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea

Ph.D., Electrical Engineering and Computer Science, Feb., 2005 $\bullet$ Dissertation Topic: ``Communication-Efficient Hardware Acceleration for Fast Functional Simulation'' $\bullet$ Advisor: Dr. Chong-Min Kyung
M.S., Electrical Engineering and Computer Science, Feb., 2000 $\bullet$ Dissertation Topic: ``Implementation of Hardware for Behavioral Model Emulator'' $\bullet$ Advisor: Dr. Chong-Min Kyung

Korea University, Seoul, Korea

B.S., Electrical Engineering, Feb., 1998

EXPERTISE

$\bullet$ FPGA-Based Functional Verification - Emulation, Prototyping, Simulation Acceleration
$\bullet$ Formal Verification - Model Checking, Coverage Analysis, Assertion-Based Design
$\bullet$ Hardware/Software Co-Verification Platform
$\bullet$ Electronic Design Automation (EDA) System Design
$\bullet$ SoC/Embedded System Design
$\bullet$ HDL-Based Digital Circuit Design
$\bullet$ Board-Level Design & Strong Hands-On Lab Skills
$\bullet$ Standard Bus System Design - PCI-Express, PCI, USB, AMBA, etc
$\bullet$ System Programming - Device Driver, Embedded OS, Firmware Programming

PROFESSIONAL EXPERIENCE

R&D Center, Dynalith System, Daejeon, Korea
Principal Engineer Jan., 2007 - Jul., 2007
Senior Engineer Mar., 2005 - Dec., 2006

FPGA-based ARM SoC verification system (sponsored by Samsung Advanced Institute of Technology)
Led the hardware development team. Implemented the general verification platform which incorporates ARM7/ARM9/ARM11 processor, audio, display, SRAM/SDRAM memory, Ethernet, DMA, timer and peripherals. Successfully demonstrated operation of 3D graphics engine and H.264 decoder on two Xilinx Virtex-4 LX200 FPGAs. Worked on top level integration of ARM-based SoC design, AMBA IP design in addition to the development of firmware and Microsoft Windows-CE BSP (Board Support Package).
PCI-Express-based HDL simulation accelerator/emulator
Implemented PCI-Express co-emulation interface for interconnecting processor to FPGA for hardware/software co-emulation system using Xilinx Virtex-5 LXT FPGA device. The co-emulation interface between testbench and DUT is composed of PLI, device driver, PCI-Express bus, PCI-Express endpoint block and transactor. Verified my design using Xilinx PCI-Express development board. Developed our own acceleration/emulation system which was connected to host computer though gigabit transmission cables.
Digital set-top box test system (sponsored by Samsung Electronics)
Developed USB 2.0 interface design for communication between host computer and set-top box tester. Carried out the logic design for Xilinx FPGA, development of Microsoft Windows USB device driver, 8051 firmware and host application program.

Korea Advanced Institute of Science and Technology, Daejeon, Korea
Student Researcher Mar., 1998 - Feb., 2005

Standard co-emulation modeling interface (SCE-MI)
SCE-MI is the standard interface between host computer and hardware emulator. Developed the automatic interface generator software using Verilog-HDL parser. Implemented C++/SystemC-based standard API library. This design automation toolkit was developed for the commercial FPGA-based hardware emulator.
FPGA-based behavioral HDL simulation engine (V2SV)
Conceived and implemented the automatic translator from behavioral testbench into synthesizable one. This method dramatically improved the performance of simulation accelerator by allowing behavioral testbench to be mapped on FPGA and directly connected to design under test.
Automatic design partitioner for efficient communication in HDL simulation accelerator (TPartition)
Conceived and implemented the automatic partitioning method and tool for reducing communication time between host processor and FPGA-based emulator. This method reduced the communication overhead by exploiting burst data transfer and parallelism, which are obtained by splitting testbench and moving a part of testbench into hardware accelerator.
HDL simulation accelerator (iPROVE)
Developed PCI-based FPGA emulator for accelerating HDL design. Developed Microsoft Windows PCI device driver, PLI/VPI/VHPI/FLI for the communication between HDL simulator and hardware emulator. Implemented API libraries for transaction-level testbench.
PCI-based in-circuit emulator (iSAVE-MP)
Carried out the schematic-level PCB design of PCI card. Implemented the interface controller for the high-speed communication channel between the PCI card and target interface module.
In-circuit emulator for C-level design verification (VirtualChip)
The rapid prototyping system for reducing the design time by verifying design in-system at the early design stage. By running algorithm part of the design on processor and mapping interface parts on FPGA array, one can get a hardware prototype in early design stage. Carried out logic and PCB design which incorporates Intel mobile Pentium processor, Altera/Xilinx FPGAs and other peripheral components.
PCI-based interface controller ASIC for high-level design verification system (SmartGlue)
Developed ASIC chips which were fabricated using 0.6um and 0.65um CMOS technology. The controller enables an Intel mobile Pentium processor to interface with target board and makes a system reconfigurable by programming FPGA on the fly.
Intel 386 processor-compatible one-chip PC (PCLET)
I carried out programmable interval timer (PIT) IP design and gate-level full-chip timing simulation and debugging.

PROFESSIONAL ACTIVITIES

EDA Conferences such as Design Automation Conference (DAC), International Conference on Computer-Aided Design (ICCAD)
Speaker and Author of Technical Papers

Accellera - Interface Technical Committee of Standard Co-Emulation Interface and Modeling Interface (SCE-MI)
Reflector present

Institute of Electrical and Electronics Engineers (IEEE)
Member Jan., 2001 - present

TEACHING EXPERIENCE

Center for SoC Design Technology, Daejeon, Korea
Seminar Presentation Dec. 21, 2006
Lectured on HW/SW co-emulation techniques using cycle-level and transaction-level interface.

Korea Advanced Institute of Science and Technology (KAIST), Deajeon, Korea
Seminar Presentation Apr., 2006
Lectured on VLSI design flow using Verilog-HDL and hands-on LAB on FPGA-based emulation practice.

Egypt Ministry of Communication & Information Technology, Software Engineering Competence Center, Cairo, Egypt
Lecturer Mar., 2006 and Sep., 2005 - Oct., 2005
Lectured on HW/SW co-simulation/emulation techniques for SoC design.

Korea Advanced Institute of Science and Technology (KAIST), Deajeon, Korea
Teaching Assistant Mar., 1999 - Jun., 2000
Introduction to VLSI systems, experiments on electric circuits

PUBLICATIONS

[Book Chapters]
Moo-Kyoung Chung, Young-Il Kim, Jae-Gon Lee, Wooseung Yang, Ando Ki, and Chong-Min Kyung, SoC Prototyping and Verification, In The Essential Issues in SoC Design: Designing Complex Systems-On-Chip, Edited by Youn-Long Steve Lin, Springer publishers, Oct. 2006.

[Journal Publications]
Young-Il Kim and Chong-Min Kyung, TPartition: Testbench Partitioning for Hardware-Accelerated Functional Verification, IEEE Design & Test of Computers, Vol. 21, No. 6, pp. 494-502, Nov./Dec. 2004.

[Conference Publications]
Young-Il Kim, Moo-Kyoung Chung, Ando Ki, and Chong-Min Kyung, Reducing Transaction-Level Modeling Effort while Retaining Low Communication Overhead for HW/SW Co-Emulation System, IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 2007

Ando Ki, Young-Il Kim, and Young-Su Kwon, Reducing Lock-Step Overhead of Hardware-Assisted Simulation Acceleration using Protocol Awareness, International System-On-Chip Design Conference (ISOCC), Seoul, Korea, Oct. 2005.

Jae-Gon Lee, Hyung-Ock Kim, Sang-Kwon Na, Young-Il Kim, and Chong-Min Kyung, iSAVE: In-System Algorithm Verifier for Early-stage SoC Verification against Actual Target Environment, International Conference on ASIC (ASICON), Shanghai, China, Oct. 2005.

Young-Il Kim, Ki-Yong Ahn, Heejun Shim, Wooseung Yang, Young-Su Kwon, Ando Ki, and Chong-Min Kyung, Automatic Generation of Software/Hardware Co-Emulation Interface for Transaction-Level Communication, IEEE International Symposium on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Taiwan, Apr. 2005.

Jae-Gon Lee, Wooseung Yang, Young-Su Kwon, Young-Il Kim, and Chong-Min Kyung, Simulation Acceleration of Transaction-Level Models for SoC with RTL sub-blocks, Asia and South Pacific Design Automation Conference (ASP-DAC), Shanghai, China, Jan. 2005.

Young-Il Kim and Chong-Min Kyung, Automatic Translation of Behavioral Testbench for Fully Accelerated Simulation, IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, USA, Nov. 2004.

Young-Il Kim, Wooseung Yang, Young-Su Kwon and Chong-Min Kyung, Communication-Efficient Hardware Acceleration for Fast Functional Simulation, IEEE/ACM Design Automation Conference (DAC), San Diego, USA, Jun. 2004, pp. 293-298.

Young-Su Kwon, Young-Il Kim and Chong-Min Kyung, Systematic Functional Coverage Metric Generation from Hierarchical Temporal Event Relation Graph, IEEE/ACM Design Automation Conference (DAC), San Diego, USA, Jun. 2004, pp. 45-48.

Young-Il Kim, Bong-Il Park, Jae-Gon Lee, and Chong-Min Kyung, SmartGlue: An Interface Controller with Auto Reconfiguration for Field Programmable Computing Machine, Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2004, pp734-736.

Young-Il Kim, Bong-Il Park, Young-Don Bae, and Chong-Min Kyung, An Interface Controller with Auto Reconfiguration for Behavioral Emulator, Korean Conference on Semiconductors, 2002.

Young-Il Kim, Bong-Il Park, Young-Don Bae, In-Cheol Park, and Chong-Min Kyung, Implementation of Controller for Behavioral Emulator, IDEC Conference, 2001.

Chang-Jae Park, Seungjong Lee, Bong-Il Park, Hoon Choi, Jae-Gon Lee, Young-Il Kim, Moo-Kyung Jung, In-Cheol Park and Chong-Min Kyung, Early in-system verification of behavioral chip models, IEEE International High Level Design Validation and Test Workshop (HLDVT), San Diego, USA, Nov. 1999.

HONORS AND AWARDS

Full Scholarship for Ph.D. Student from Dynalith System, Korea, 2000 - 2005.
First Place Award from IDEC (Integrated Circuit Design Education Center)/KAIST programming logic design contest, Korea, 1999.
Full Scholarship for M.S. Student from Ministry of Science and Technology, Korea, 1998 - 2000.
Honor Scholarships from Korea University, Korea, Spring 1997 and Fall 1997.
Semester High Honors from Korea University, Korea, Fall 1996 and Spring 1997.

TECHNICAL SKILLS

$\bullet$ Languages: C/C++, Assembly language, SystemC, SystemVerilog, Verilog, VHDL, EDIF, Spice, Perl, ML, Tcl/Tk
$\bullet$ Logic implementation: Modelsim, NC-SIM, VCS, Mentor Leonardo Spectrum, Synopsys Design Compiler, Synplicity Synplify Pro, Xilinx XST, Xilinx ISE, Altera Quartus II
$\bullet$ Hardware interface design experience: PCI-Express, PCI, USB2.0, USB OTG, SDR SDRAM, DDR2 SDRAM, SRAM, Ethernet, UART, PS/2, Bluetooth
$\bullet$ Hardware/software interface: PLI, VPI, VHPI, FLI, SCE-MI
$\bullet$ Physical analyzer: Oscilloscope, Logic Analyzer, Signal Generator, Spectrum Analyzer
$\bullet$ Firmware programming: ARM ADS, ARM RVDS, Keil compiler, GNU GCC
$\bullet$ Device driver development: Microsoft DDK, Microsoft Platform Builder, NuMega SoftICE
$\bullet$ JTAG debugger (For software development): ARM RealView ICE, Lauterbach Trace32
$\bullet$ JTAG debugger (For hardware development): Xilinx Chipscope
$\bullet$ PCB design: Cadence OrCAD

REFERENCES

Available upon request

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