Re: "ITC'99" Benchmarks

[Sitaram Yadavalli <syadava@cadev6.intel.com>]

Before we endorse any circuit as a benchmark we should put in place a 
ballot process so that we all agree that each of the benchmarks is at least
complete, in that it has all the requisite material(s) coming with it. E.g.
A minimum standard would require that a benchmark has synthesizable RTL in
Verilog AND VHDL, it has the corresponding gate-level descriptions with a 
standard cell library AND also with structural Verilog primitives. It should
have gone through some amount of design verification to ensure that the gate
level design corresponds to the RTL. It should have a Verilog Test Bench with
non-scan test vectors. The corresponding set can also be provided in a simple
format like a table.

A behavioral description of the design may also be given in Verilog or VHDL. 
One major problem with high level descriptions in non-standard formats is that
they all end up as different designs/circuits and comparison of results becomes
a nightmare (especially for Ph.D Students!)

I am sure there are lots of specific requirements that these may need to meet
at a minimum.

-Sitaram