Introduction

As the minimum feature size further decreases, multiple patterning lithography (MPL) has become one of the most viable solutions to sub-14nm half-pitch patterning. Multiple patterning lithography consists of double, triple, or quadruple patterning. In multiple patterning lithography manufacturing process, there are several exposure/etching steps, through which the layout can be produced. The advantage of this process is that the effective pitch can be improved, which improves the lithography resolution. The key challenge of multiple patterning lithography is the layout decomposition, where input layout is divided into several masks. When the distance between two input features is less than minimum coloring distance , they need to be assigned to different masks to avoid a coloring conflict. Sometimes coloring conflict can be also resolved by inserting stitch to split a pattern into two touching parts. However this introduces stitches, which lead to yield loss because of overlay error. Therefore, two of the main objectives in layout decomposition are conflict minimization and stitch minimization. We present a high performance MPL-Decomposer to resolve the layout decomposition problem for multiple patterning lithography.

MPL Excutables

• Version 2.0: ICCAD’11 excutables

• Version 3.1: ICCAD’13 excutables

• Version 3.7: TCAD’15 excutables Results: ISCAS GDSII

SimpleMPL Executables

• Version 1.0: SPIE’16 executables

Benchmarks

• ISCAS 85/89 Benchmarks: GDSII format

• ISCAS 85/89 Benchmarks: ASCII format

Publications

• Yibo Lin, Xiaoqing Xu, Bei Yu, Ross Baldick, and David Z. Pan, “Triple/Quadruple Patterning Layout Decomposition via Novel Linear Programming and Iterative Rounding”, SPIE Advanced Lithography Conference, San Jose, CA, Feb. 21-25, 2016 (to appear)

• Bei Yu and David Z. Pan, “Layout Decomposition for Triple Patterning”, in Encyclopedia of Algorithms, M.-Y. Kao eds., Springer, 2015.

• Bei Yu, Kun Yuan, Duo Ding, and David Z. Pan, “Layout Decomposition for Triple Patterning Lithography”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, no.3, pp.433-446, 2015.

• Bei Yu and David Z. Pan, “Layout Decomposition for Quadruple Patterning Lithography and Beyond”, ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, June 1-5, 2014 .

• Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, and David Z. Pan, “A High-Performance Triple Patterning Layout Decomposer with Balanced Density”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, November 18-21, 2013.

• Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding and David Z. Pan, “Triple Patterning Lithography Layout Decomposition”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011. (William J. McCalla Best Paper Award Nomination)

Contact

MPL-Decomposer is developed by Yibo Lin, Bei Yu, and Prof. David Z. Pan. Please contact us with any bug reports and comments.

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