RegPlace: A High Quality Structured ASIC Placement Tool   

Authors: Ashutosh Chakraborty, Anurag Kumar and Prof. David Z. Pan

Formats & Benchmarks


RegPlace is a new placement tool for structured ASIC platforms.  Structured ASIC consists of a structurally regular "tile" which is replicated over the layout of the chip.  Physical platform of structured ASIC have very strict clock constraints, site legality and geometrical constraints.  Using tools that are meant for cell-based design for structured ASIC can lead to low quality placement results.  RegPlace incorporates several ideas to solve structured ASIC problem such as: 1) Virtual platform and RTL generation to use any existing global placer to get geometric proximity information, 2) Solution mapping from virtual platform to real platform by interleaving region expansion and FM style cut minimization, 3) ILP based intra-tile clock and site legalization, and 4) Multi-level wirelength reduction heuristics.


NOTE: The most current version is RegPlace2.

  1. RegPlace1 is the Grand prize winner ($25000) for the eASIC Placement Design Challenge.  Code frozen on 28th December 2008.  Source code release of RegPlace1 can be downloaded here.

  2. RegPlace2 improves over version 1 by incorporating ILP formulation for "tile" level clock assignment, network flow based high-level density equalization and better wire-length reduction heuristics.  On an average, RegPlace2 outperforms RegPlace1 by 6% better wire-length consuming 10% less CPU time.  RegPlace2 binary is available here.

Formats & Benchmarks

          The traditional Bookshelf format is extended by adding two new files.  First is .props file which identifies each type of cell and clock type incident to it.  Second file is .region file which has hierarchical information regarding the geometry and clock constraints of each region on this chip.

        Tool outputs final .pl file containing the final placement.  See Bookshelf format for description of .pl file format.  Some intermediate images are also dumped.   

          Placement Contest benchmarks as released by eASIC Corporation.  (In case link broken, try local copy here).

          A compiled C++ program to evaluate the validity of placement solution w.r.t. clock, site and geometrical legality constraints can be found here.

Awards & Publications

 Grand Prize in eASIC Placement Challenge ($25000)


Performance & Results

Coming soon.


              CAPO: Prof. Igor Markov:

              mPL6: Prof. Jason Cong:




 last updated by 11 March 2009 by Ashutosh Chakraborty