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It is widely recognized that
process variation is emerging as a fundamental challenge to IC design in scaled
CMOS technology; and it will have profound impact on nearly all aspects of
circuit performance. While some of the negative effects of variability can
be handled with improvements in the manufacturing process, the industry is
starting to accept the fact that some of the effects are better mitigated
during the design process. Handling variability in the design process will
require accurate and appropriate models of variability and its dependence
on designable parameters (i.e. layout), and its spatial and temporal
distributions. It also requires carefully designed test structures and
proper statistical data analysis methods to extract meaningful models from
large volumes of silicon measurements. The resulting compact modeling of
systematic, random, spatial, and temporal variations is essential to
abstract the physical level variations into a format the designers (and
more importantly, the tools they use) can utilize. This workshop provides a
forum to discuss current practice as well as near future research needs in
test structure design, variability characterization, compact variability
modeling, and statistical simulation.
Key Topics
 Physics mechanisms and
technology trends of device-level variations
First-principles
simulation methods for predicting variability
Time-dependent variation and their interaction with other
variation sources
Compact modeling of
variations in devices and interconnect
Device and circuit level
modeling techniques
Test structure design for
variability
Variability
characterization, bounding and extraction
Statistical data analysis and model extraction methods
Novel implementation and
simulation techniques for dealing with variability
Tentative Agenda (talk
abstract in PDF, poster
abstract in PDF)
8:30 – 8:40am Opening Remarks
8:40 – 10:10am Session I: Process
Variability in Scaled VLSI Design
Duane Boning
(MIT): Test Structures, Circuits, and
Extraction Methods for Determining Pattern Density Effects
Toshiro Hiramoto (Univ. of Tokyo): Measurements and Post-Fabrication Self-Improvement of SRAM Cell
Stability
Shawn
Blanton (CMU): Improving Design,
Manufacturing, and Even Test through Test-Data Mining
10:10 – 10:30am Morning Break/Discussion
10:30 – 12:00pm Session II: Analog Design Variability
Brandt
Braswell (Freescale): The Impact of Process Variability as It Relates to Modeling and
Design in Advanced CMOS Technologies
Debarshi Basu (TI): Characterization and Modeling of MOSFET Noise in Sub-threshold Region
Abhijit Chatterjee (GaTech): Handling
Process Variability: Self-Testing and Self-Tuning Mixed-Signal/RF Circuits and Systems
12:00 – 1:30pm Lunch
1:30 – 3:30pm Session III:
Variability in 3D Integration
Riko Radojcic (Qualcomm): New Sources of Variability in 3D TSS Technologies
Paul Franzon (NCSU): Managing Variability in 3D IC
Azad Naeemi (GaTech): Interconnect Networks in 2D and 3D Nanoelectronic
Systems
Victor Moroz
(Synopsys): TSV Stress Effects for Digital and Analog
Circuits
3:30 – 5:00pm Poster Session and Discussion
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