Fall 2017 (Tentative, may be updated)


Please discuss your project plans with the instructor.

The project will let you utilize the design skills acquired in the class (particularly from Labs 1-3) to design a module of interest to you. The projects can focus on different aspects of VLSI Design.

Some designs can be at the RT level, and include synthesis, simulation based verification, static timing analysis and area estimation. You may add new cells to the given library but need to add layout, verification and timing models. There is no need to do the layout of the complete design but you need to do an area estimation using the floorplan.

Other projects can start at the schematic level, for example, those dealing with high performance domino-logic circuits. These would involve custom modules (verified using SPICE simulation), schematic entry, logic simulation, physical design, performance/power estimation, etc.


Some suggestions for possible projects are provided here.

PROJECT SUGGESTIONS (these are just suggestions, and the document will be updated during the semester; try to come up with your own ideas for a module of interest to you and your team, or please talk to Prof. Abraham or the TAs)