- Applied "functional formal verification" (equivalence checking and
model checking) to some extent on approximately 40 design components,
including portions of the instruction unit, floating point unit, control
logic, memory subsystem and I/O chips
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Found more than 200 design flaws at various stages
and of varying complexity
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At least one bug was found by almost every
application of formal verification
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Estimate: 15% of bugs would have evaded
simulation
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Some of the bugs literally escaped 1-2 years of
simulation
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Found that application of formal techniques by
designers themselves, using formal team as consultants, was very
fruitful
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