 |
Array Verification at Motorola |
- All arrays on latest Power-PC processor verified using VERSYS
- Complete array verification took about 8%-10% of array design time
- Properties proved on RTL and transistor-level models
- Bugs found during custom array equivalence checking
- Incorrect clock regenerators feeding latches
- Control logic errors in READ/WRITE enables
- Violation of "one-hot" property assumptions
- Scan chain hookup errors
- Potential circuit-related problems such as glitches and races
|
Hardware Verification
- Application of formal techniques to chip designs
|
Slide 28 of
30 |