Checking the Logic of the Entire Design

Is there a formal verification technique which can be applied to the entire chip?

• There is only one approach which will scale with the design: Simulation
• Most common technique used in industry today
• Cycle-based simulation can exercise the design for millions of cycles
• Unfortunately, there are no good measures of coverage, and the question of when to stop simulation is an open one
• Emulation is a related approach to speed up the effort (used for verifying the first Pentium processor)
• Developing another accurate model could be an issue