Selected Publications
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Patents
- US Patent 9,824,243; Model-based Runtime Detection of Insecure
Behavior for Hardware System-of-Chip with Security Requirements
- US Patent 9,043,737; Hardware Integrated circuit design verification through
forced clock glitches
- US Patent 9,092,567; Systems and methods for analyzing transactions
in a computer system
- US Patent 9,069,762; Equivalence classes over parameter state space
- US Patent 9,002,694; Verification of hardware design derived from power intent
- US Patent 8,584,063; Assertion-based hardware design partitioning
- US Patent 8,555,226; Automatic verification of dependency
- US Patent 8,234,618; Trace reconstruction for silicon validation of
asynchronous systems-on-chip hardware
- US Patent 8,050,904; System and method for circuit symbolic timing
analysis of hardware circuit designs
- US Patent 7,945,418; Stream based stimulus definition and delivery
via interworking
- US Patent 7,650,579; Model correspondence method and device
- US Patent 7,360,183; Design analysis tool and method for deriving
correspondence between storage elements of two memory models
- US Patent 6,952,812; Design analysis tool for path extraction and
false path identification and method thereof
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US Patent pending: Autonomous Hardware for Application Power Usage
Optimization
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US Patent pending: Fault Detection for Safety-Critical Hardware
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US Patent pending: Hardware Monitor for Ultra-Secure Integrated
Circuits
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Refereed Archival Journal Publications & Book Chapters
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Kuo-Kai Hsieh, Wen Chen, Jayanta Bhadra, and Li-C. Wang,
"Data-Driven Test Plan Augmentation for Platform Verification",
IEEE Design and Test of Computers (IEEE D&T), 2017.
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Jayanta Bhadra, Magdy Abadir, and Li-C. Wang,
"Guest Editors' Introduction: Emerging Challenges and Solutions
in SOC Verification", IEEE Design and Test of
Computers (IEEE D&T), Volume: 34, Number: 5, May/June 2017.
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Wen Chen, Sandip Ray, Magdy Abadir, Jayanta Bhadra, and Li-C. Wang,
"Challenges and Trends in Modern SOC Design Verification",
IEEE Design and Test of Computers (IEEE D&T), 2017.
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Wen Chen, Jayanta Bhadra, and Li-C. Wang,
"System-on-Chip Security and Debug",
book chapter in "Fundamentals of IP and SoC Security - Design, Verification and Debug",
edited by Swarup Bhunia, Sandip Ray and Susmita Sur-Kolay.
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Sandip Ray, Jayanta Bhadra, Magdy Abadir, Li-C. Wang, and
Aarti Gupta,
"Introduction to Special Section on Verification Challenges
in the Concurrent World",
ACM Transactions on Design Automation of Electronic Systems,
Volume: 17, Number: 3, June 2012.
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Jayanta Bhadra, Ekaterina Trofimova, and Magdy Abadir,
"Validating Power Architecture (TM) Technology-based
MPSoCs through Executable Specifications",
IEEE Transactions on VLSI Systems (TVLSI),
Volume: 16, Number: 4, April 2008.
(download PDF)
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Jayanta Bhadra, Magdy Abadir, and Li-C. Wang,
"Guest Editors' Introduction: Attacking Functional Verification
through Hybrid Techniques", IEEE Design and Test of
Computers (IEEE D&T), Volume: 24, Number: 2, March/April 2007.
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Jayanta Bhadra, Magdy Abadir, Li-C. Wang, and Sandip Ray,
"A Survey of Hybrid Techniques for Functional Verification",
IEEE Design and Test of Computers (IEEE D&T),
Volume: 24, Number: 2, March/April 2007.
(download draft PDF)
(details)
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Jayanta Bhadra, Magdy Abadir, David Burgess, and Ekaterina Trofimova,
"A Bottom-up Approach in Automated Embedded Memory Model
Generation for High Performance Microprocessors",
IEE Proceedings of Computer and Digital
Techniques (CDT), Volume: 153, Number: 5, September 2006.
(download PDF)
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Jayanta Bhadra, "Theory and Practice of Automatic Design Constraint
Generation", IEE Proceedings of Computer and Digital Techniques
(CDT), Volume: 153, Number: 1, January 2006.
(download PDF)
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Jayanta Bhadra, Andrew Martin, and Jacob Abraham,
"A Formal Framework for Verification of Embedded Custom Memories of
The Motorola PowerPC MPC7450 Microprocessor",
Formal Methods in System Design (FMSD), Volume: 27, Numbers: 1 & 2,
September 2005.
(download PDF) Acceptance rate: 6%
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Jayanta Bhadra, Magdy Abadir, and Nari Krishnamurthy,
"Enhanced Equivalence Checking: Toward a Solidarity of Functional
Verification and Manufacturing Test Generation",
IEEE Design and Test of Computers (IEEE D&T), Volume: 21, Number: 6,
November/December 2004.
(download PDF)
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Vivek Vedula, Jacob Abraham, Jayanta Bhadra, and Raghuram Tupuri,
"A Hierarchical Test Generation Approach Using Program Slicing
Techniques on Hardware Description Languages",
Journal of Electronic Testing: Theory and Applications (JETTA),
Volume: 19, Number: 2, April 2003.
(download PDF)
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Refereed Conference/Workshop Publications
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"Extendibility in Automotive Security: Current Practice and
Challenges", with S. Ray, W. Chen and
M. A. Faruque
at the Design Automation Conference (DAC invited paper),
June 2017.
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"Learning to Produce Direct Tests for Security Verification
Using Constrained Process Discovery", with
Kuo-Kai Hsieh, Wen Chen and Li-Chung Wang
at the Design Automation Conference (DAC), June 2017.
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"Automatic Investigation of Power Inefficiencies", with
Kuo-Kai Hsieh, Monica Farkash, Wen Chen and Li-Chung Wang and Wen Chen
at the Design and Verification Conference (DVCon), March 2017.
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"Feature Extraction from Design Documents to Enable Rule
Learning for Improving Assertion Coverage", with
Kuo-Kai Hsieh, Sebastian Siatkowski, Wen Chen and Li-Chung Wang
at the Asia and South-Pacific Design Automation Conference (ASPDAC),
January 2017.
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"Security Challenges for Mobile and IoT Devices", with
Sandip Ray
at the IEEE SOC Conference (SOCC), September 2016.
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"Striking a Balance Between SOC Security and Debug Requirements", with
Wen Chen
at the IEEE SOC Conference (SOCC), September 2016.
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"Addressing Information Flow Properties in Hardware
Security Verification", with
Wen Chen, Monica Farkash and Jing Huang,
at the Constraints in Formal Verification (CFV workshop
@ICCAD), Austin, TX, November, 2015
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"On Application of Data Mining in Functional Debug", with
K.-K. Hsieh, W. Chen, L.-C. Wang,
at the International Conference on Computer Aided Design
(ICCAD), San Jose, CA, November, 2014
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"Simulation Knowledge Extraction and Reuse in Constrained Random
Processor Verification", with
Wen Chen, Li-C. Wang, and Magdy Abadir,
at the Design Automation Conference
(DAC), Austin, TX, June, 2013
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"Automatic Verification of Dependency", with
Shaun Feng at the Design Automation Conference
(DAC), Austin, TX, June, 2013 (Designer Track paper)
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"Assertion based design Partition", with
Shaun Feng and Ross Patterson at the Design Automation Conference
(DAC), Austin, TX, June, 2013 (Designer Track paper)
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"TUTORIAL: Modeling, Abstraction, and Verification of Non-Volatile
Memories", with
Sandip Ray
at the Design Automation Conference (DAC), Austin, TX, 2013
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"Novel Test Analysis to Improve Structural Coverage -- A
Commercial Experiment", with
Wen Chen, Li-C. Wang, and Magdy Abadir,
at the International Symposium on VLSI Design, Automation & Test
(VLSI-DAT), Hsinchu, Taiwan, April, 2013
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"Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS
Designs - The First Step", with Chia-Ling (Lynn) Chang, Charles
H.-P. Wen at the Design, Automation and Test in Europe (DATE), 2013
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"Novel Test Detection to Improve Simulation Efficiency -- A
Commercial Experiment", with
Wen Chen, Nikolas Sumikawa, Li-C. Wang, Shaun Feng, and Magdy Abadir,
at the International Conference on Computer Aided Design (ICCAD),
San Jose, CA, November 2012.
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"An Intelligent Analysis of Iddq Data for Chip Classification in
Very Deep-Submicron (VDSM) CMOS Technology", with
C.-L. Chang, C.-C. Chang, H.-L. Chan, Charles H.-P. Wen
at the Asia Pacific Design Automation Conference (ASPDAC'12), Syndey,
Australia, January 2012.
(WINNER OF THE BEST PAPER AWARD)
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"A Unified Formal Framework for Analyzing
Functional and Speed-path Properties", with
Oswaldo Olivo, Sandip Ray and Vivek Vedula,
at the Workshop on Microprocessor Test and Verification (MTV'11),
Austin, TX, December 2011.
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"EDA Gaps and Requirements for Functional Verification", with
Matthias Bauer,
Thomas Dillinger,
Bjorn Fjellberg,
Kim Joonyoung,
David Lacey,
Jing Li,
Khankap Mounarath,
Christopher J. Spandikow and
Thomas Harms,
User Session at the Design Automation Conference (DAC'11), San Diego,
CA, June 2011.
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"Embedded Tutorial: Modeling, Abstraction and Verification of
Industrial Flash Memories", with Sandip Ray, International
Symposium on Quality Electronic Design (ISQED'11), Santa Clara,
CA, March 2011.
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"A Kernel-Based Approach for Functional Test Program
Generation", with P.-H. Chang and L.-C. Wang, International
Test Conference (ITC'10), Austin, TX, October 2010.
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"Modeling and Verification of Industrial Flash
Memories", with Sandip Ray, Thomas Portlock and Ronald Syzdek,
International Symposium on Quality
Electronic Design (ISQED'10), San Jose, CA, March 2010.
- "Simulation of a heterogeneous system at multiple levels of
abstraction using Rendezvous based modeling", with Vyas
Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Microprocessor Test and
Verification (MTV'09), Austin, TX, December 2009.
- "Symbolic Execution Engine to Explore Path Feasibility in
Assembly Programs", with Subodh Sharma, Todd Dukes and Ganesh
Gopalakrishnan, Microprocessor Test and Verification (MTV'09), Austin,
TX, December 2009.
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"On Soft Error Rate Analysis of Scaled CMOS Designs -- A
Statistical Perspective", with Huan-Kai Peng and Charles Wen,
International Conference on Computer-Aided Design (ICCAD'09), San
Jose, CA, November 2009.
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"Speeding up Bounded Sequential Equivalence Checking with
Cross-timeframe State-Pair Constraints from Data Learning", with
Lynn Chang and Charles Wen, International Test Conference (ITC'09),
Austin, TX, November 2009.
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"Portable Simulation/Emulation Stimulus on an Industrial-Strength
SoC", with C. Wen, M. Bose, F. Torres, R. Srivastava and J. Ruiz in
the International Test Conference (ITC'09), Austin, TX, November
2009. (poster)
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"Lyra: A Rendezvous-based High Level Modeling Approach for Digital
Hardware", with V. Venkataraman, D. Wang, W. Qin and M. Bose,
International Conference on Formal Methods and Models for Codesign
(MEMOCODE), 2009.
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"Synthesis-oriented scheduling of multiparty rendezvous
in Transaction Level Models", with V. Venkataraman, D. Wang,
A. Mahram, W. Qin and M. Bose, IEEE Computer Society
Annual Symposium on VLSI (ISVLSI'09), Tampa, FL, May 2009.
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"Accelerating Multi-party Scheduling for Transaction-level
Modeling", with D. Wang, V. Venkataraman, Z. Wang, W. Qin,
H. Wang and M. Bose, Great Lakes Symposium on VLSI (GLSVLSI'09),
Boston, MA, May 2009.
(download PDF)
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"An Abstraction Mechanism to maximize stimulus
portability across RTL, FPGA, Software models and
Silicon of SoCs", with M. Bose, P. Naphade,
H. Miller, International Symposium on Quality
Electronic Design (ISQED'09), San Jose, CA, March 2009.
(download PDF)
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"Abstracting and Verifying Flash Memories",
with S. Ray, Non-Volatile Memory Technology Symposium
(NVMTS'08), Pacific Grove, CA, November, 2008.
(details)
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"A Mechanized Refinement Framework for Analysis of
Custom Memories", with S. Ray, Formal
Methods in Computer-Aided Design (FMCAD'07), Austin, TX,
November 2007.
(details)
(BEST PAPER CANDIDATE)
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"An Incremental Learning Framework for Estimating
Signal Controllability in Unit-Level Verification",
with Charles Wen and L. Wang, International Conference on
Computer-Aided Design (ICCAD'07), San Jose, CA,
November, 2007.
(download PDF)
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"Enhancing signal controllability in functional testbenches
through automatic constraint extraction",
with O. Guzey and L. Wang,
International Test Conference (ITC'07), Santa Clara, CA,
October, 2007.
(download PDF)
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"Directed Micro-architectural Test Generation: A Case Study",
with H.-M. Koo, P. Mishra, and M. S. Abadir, International
Workshop on Microprocessor Test and Verification (MTV'06),
Austin, TX, December 2006.
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"A Trace-Driven Validation Methodology for
Multi-Processor SoCs", with Ekaterina Trofimova,
Leonard Giordano, Magdy Abadir, IEEE International System on Chip
Conference (SOCC'06), Austin, TX, September 2006.
(download PDF)
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"The impact of Equivalence Checking and DFT on the testbench
conversion problem", with Ekaterina Trofimova, The Freescale
Semiconductor Design-For-Test Conference (DFT'05), Austin, TX,
December 2005. (invited paper)
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"Automatic Generation of High Performance Embedded Memory Models for
PowerPC Microprocessors" , with Ekaterina Trofimova, David Burgess,
and Magdy Abadir, Microprocessor Test and Verification (MTV'05),
Austin, TX, November 2005.
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"Establishing Latch Correspondence for Embedded Circuits of PowerPC
Microprocessors" , with Himyanshu Anand, Alper Sen,
Kenneth Davis, and Magdy Abadir, IEEE High Level Design Validation and
Test (HLDVT'05), Napa, CA, November 2005.
(download PDF)
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"genCRAM: Testview Generator for Embedded Memories", with
Ekaterina Trofimova, The Freescale Semiconductor Design-For-Test
Conference (DFT'04), Austin, TX, December 2004. (invited paper)
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"Formal Verification of a System-on-Chip Using Computation Slicing"
, with Alper Sen, Vijay Garg and Jacob Abraham,
The International Test Conference (ITC'04), Charlotte, NC, October 2004.
(download PDF)
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"Towards the Complete Elimination of Gate/Switch Level Simulations"
, with Nari Krishnamurthy, Magdy Abadir and Jacob Abraham,
The International Conference on VLSI Design (VLSI Design'04),
Bombay, India, January 2004.
(download PDF)
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"Model Checking Security Protocols using Pre-Configuration",
with Kyoil Kim, and Jacob Abraham, The International Workshop
on Information Security Applications (WISA'03), Jeju Island, Korea,
August 2003.
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"Automatic Validation of Chip-level Assertions in Verifying High
Performance Circuits",
with Narayanan Krishnamurthy, The IEEE International Workshop
on Microprocessor Test and Verification (MTV'03), Austin, TX,
May 2003.
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"A Methodology for Validating Manufacturing Test Vector Suites
for Custom Designed Scan-Based Circuits",
with Narayanan Krishnamurthy and Magdy Abadir, The IEEE
International Workshop on Microprocessor Test and Verification (MTV'03),
Austin, TX, May 2003.
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"Automatic Generation of Design Constraints in
Verifying High Performance Embedded Dynamic Circuits",
with Narayanan Krishnamurthy, The
International Test Conference (ITC'02), Baltimore, MD,
October 2002.
(download PDF)
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"Program Slicing for Hierarchical Test Generation",
with Vivekananda Vedula and Jacob Abraham, The
IEEE VLSI Test Symposium (VTS'02), Monterey,
CA, April-May 2002.
(download PDF)
(WINNER OF THE BEST PAPER AWARD)
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"Is State Mapping Mapping Essential for Equivalence Checking Custom
Memories in Scan-Based Designs?",
with Narayanan Krishnamurthy, Magdy Abadir, and Jacob Abraham,
The IEEE VLSI Test Symposium (VTS'02), Monterey,
CA, April-May 2002.
(download PDF)
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"A Language Formalism to verify PowerPC(TM) Custom Memories
Using Compositions of Abstract Specifications",
with Andrew Martin and Jacob Abraham, The IEEE
International High Level Design Validation and Test Workshop (HLDVT'01),
Monterey, CA, November 2001.
(download PDF)
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"Using Abstract Specifications to verify
PowerPC(TM) Custom Memories by Symbolic Trajectory Evaluation",
with Andrew Martin, Magdy Abadir and Jacob Abraham, The
Eleventh Advanced Research Working Conference on Correct Hardware Design and
Verification Methods (CHARME'01), Edinburgh, Scotland, September 2001.
(download PDF)
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"Full Chip False Timing Path Identification: Applications to the
PowerPC(TM) Microprocessors",
with Jing Zeng, Magdy Abadir and Jacob Abraham,
The Design, Automation and Test in Europe (DATE'01)
Conference and Exhibition, Munich, Germany, March 2001.
(download PDF)
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"Automatic Formal Verification of Interacting Finite State Machines",
with Rob Sumners and Jacob Abraham, The
Eighth International Conference on Computer Aided Systems Theory
(EUROCAST'01), Canary Islands, Spain, February 2001.
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"An Abstraction Technique for Formal Verification of Properties on a
Network of Interacting Finite State Machines",
with Rob Sumners and Jacob Abraham as Technical Publication
of the Computer Engineering Research Center, # TR-JAA-00-01,
Department of Electrical and Computer Engineering, The University of
Texas at Austin, October 2000.
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"Full chip false timing-path identification",
with Jing Zeng, Magdy Abadir and Jacob Abraham,
The IEEE Workshop on Signal Processing Systems
(SIPS'00) Design and Implementation, Lafayette, LA,
October 2000.
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"A quick and inexpensive method to identify false critical
paths using ATPG techniques: an experiment with a PowerPC(TM)
microprocessor",
with Magdy Abadir and Jacob Abraham
The IEEE Custom Integrated Circuits
Conference (CICC'00), Orlando, FL, May 2000.
(download PDF)
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"A quick and inexpensive method to identify false critical
paths using ATPG techniques",
with Magdy Abadir and Jacob Abraham
The First IEEE Latin American Test Workshop
(LATW'00), Rio de Jeneiro, Brazil, March 2000.
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"Automatic Validation Test Generation using Extracted Control
Models" , with Rob Sumners and Jacob Abraham
The International Conference on VLSI Design (VLSI Design'00),
Calcutta, India, January 2000.
(download PDF)
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"Improving Witness Search using Orders on States",
with Rob Sumners and Jacob Abraham, The
International Conference on Computer Design (ICCD'99), Austin,
TX, October 1999.
(download PDF)
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"Verification of
a Traffic Light Controller",
with Indrajit Chakrabarti, Dipankar Sarkar and Arun K. Majumdar,
The Third Asia-Pacific Conference
on Hardware Description Languages (APCHDL'96),
Bangalore, India, January 1996.
Last updated: December 2017.
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