ITC99 Benchmark Home Page
The benchmark effort needs your help! Volunteers are need to:
Characterize the benchmarks.
Synthesize the RTL only benchmarks.
Translate Verilog to VHDL and vice versa.
Map proprietary libraries.
Remove scan where necessary. (Both scan and non-scan versions will be available).
Insert DFT and/or run ATPG on the benchmarks with research tools.
Present results at ITC.
Please contact Scott Davidson
Presentation on Benchmark Characteristics.
The presentation on the characteristics of the benchmarks given at the 6th
International Test Synthesis Workshop is here.
More Details on Benchmarks.
A writeup giving more details on the benchmarks, including links to some of them, is here.
Minutes of the Benchmark Meeting at ITC
The minutes from a meeting on benchmarking held at the 1998 International
Test Conference are available here.
ITC'99 Benchmarks an Official TTTC Activity
The benchmarking effort is now an official activity of the IEEE
Computer Society Test Technology
Technical Committee. Scott Davidson has been appointed
Vice Chair of the Test Synthesis TAC for this effort.
What are the ITC99 Benchmarks?
They are a set of benchmark circuits, gathered from many companies in the
electronics business, that are meant to be used for experimentation on
Design for Testability (DFT) and Automatic Test Pattern
Generation (ATPG). The benchmarks and first DFT and
ATPG results will be presented at the 1999 International Test Conference
in Atlantic City, New Jersey
Why New DFT Benchmarks?
Simply because the last set, first presented at ISCAS'89, are almost ten
years old. Those benchmarks, though challenging in their day, are
too small and simple to drive progress in DFT and ATPG. They are
also presented at the gate level, while most designs today are done in
RTL. Visit the documents page for more justification.
How Can I Help?
Things to Do
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Thanks to Jacob Abraham and the University of Texas at Austin for providing space for this page.