IEEE/ACM Workshop on Variability Modeling and Characterization

(VMC) 2017

November 16,  2017

Irvine, CA

Registration through ICCAD

(Programs of previous workshops are available: 2016, 2015, 2014, 2013, 2012, 2011, 2010, 2009, 2008)

Call for Abstract: submission due on Oct. 10, 2017; acceptance on Oct. 17, 2017; accepted abstract will be presented at the poster session

Variability has emerged as a fundamental challenge to IC design in scaled CMOS technology; and it has profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled via improvements in the manufacturing process, comprehensive methods are necessary to assess and manage the negative effects of variability, which in turn requires accurate and tractable variability models. The goal of the VMC workshop is to provide a forum for theoreticians and practitioners to freely exchange opinions on current practices as well as future research needs in variability modeling and characterization. The workshop organizers strongly encourage the submission of early results in the related topics. The submissions will be evaluated by the Technical Program Committee, and the author(s) of the accepted submissions are expected to present the results in the format of posters and few-minutes introductory presentations at the workshop. Proceedings of the workshop are limited to the attendees.

Key Topics

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Fundamental physics of device variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Compact variability modeling development and applications

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Statistical extraction of variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Variability test structure design and calibration

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Design interface with manufacturing and solutions for variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Variability issues in emerging semiconductor technology

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Temporal variability issues

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Reliability considerations that may be closely related to variability

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\dot.jpg   Variability in computing and systems

Agenda

8:45 – 9:00am        Opening Remarks

Session 1: Frontiers of Computing

9:00 – 9:45am        Morning Keynote: Fadi Kurdahi (UC Irvine)

Revisiting the Perfect Chip Paradigm: Cross-Layer Approaches to Designing and Monitoring Reliable Systems using Unreliable Components

9:45 – 10:15am      Vijay Narayanan (Pennsylvania State University)

Is it Logic or Memory? - Blurring the gap

10:15 – 10:45am    Tajana Simunic Rosing (UC San Diego)

Increasing computational efficiency with novel computing paradigms

10:45 – 11:00am    Break

Session 2: MEMS and Optics

11:00 – 11:30am    Yoshio Mita (University of Tokyo)

Visualizing is Believing - Test Structures for Deep-Etched High Aspect Ratio MEMS Process and Device Characterization

11:30 – 12:00am    Peter McMahon (Stanford University)

Computing using networks of optical parametric oscillators

12:00 – 1:00pm      Lunch

Session 3: Memory of the Future

1:00 – 1:45pm        Afternoon Keynote: Hai Li (Duke University)

Enhance the Reliability and Scalability of Memristor-based Neuromorphic Systems

1:45 – 2:15pm        Vivek Seshadri (Microsoft)

Processing Using Memory: Mechanisms, Benefits, and Challenges

2:15 – 2:45pm        Haitong Li (Stanford University)

3D Vertical Resistive RAM (VRRAM) for In-Memory Computing          

2:45 – 3:00pm        Afternoon Break/Discussion

Session 4: Conclusionary Talk and Posters

3:00 – 3:30pm        Hidetoshi Onodera (Kyoto University)

Toward Minimum Energy Operation of Voltage-Scaled Circuits

3:30 – 4:00pm        Poster Presentations (time equally divided for each poster)

4:00 – 4:30pm        Poster Session and Networking

Technical Program Committee

Co-chairs:   Abe Elfadel, Masdar Institute, Abu Dhabi

                     Takashi Sato, Kyoto University, takashi AT i DOT kyoto-u DOT ac DOT jp

                     Rasit O Topaloglu, IBM, rasit AT us DOT ibm DOT com

 

Yu (Kevin) Cao, Arizona State University, USA

Chris Kim, University of Minnesota, USA

Colin McAndrew, Freescale Semiconductor, USA

Subhasish Mitra, Stanford University, USA

Hidetoshi Onodera, Kyoto University, Japan

David Z. Pan, University of Texas at Austin, USA

Vijay Reddy, Texas Instruments, USA

 

Sponsors:

Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\ieee.jpg          Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\edsjpeg.jpg     Description: Description: Description: Description: Description: Description: Description: C:\Paper Review\Modeling\2012\webpage\acm.jpg   Description: Description: Description: Description: Description: Description: Description: SRC_GRC_logo_c.jpg            

Last updated on August 22, 2017. Contents subject to change. All rights reserved.