Re: Exchange of mail on Test benches and benchmark requirements

["Luis Basto" <lbasto@pirates.amd.com>]

> From: Sitaram Yadavalli <syadava@cadev6.intel.com>
>
> Before we endorse any circuit as a benchmark we should put in place a
> ballot process so that we all agree that each of the benchmarks is at least
> complete, in that it has all the requisite material(s) coming with it. E.g.
> A minimum standard would require that a benchmark has synthesizable RTL in
> Verilog AND VHDL, it has the corresponding gate-level descriptions with a
> standard cell library AND also with structural Verilog primitives. It should
> have gone through some amount of design verification to ensure that the gate
> level design corresponds to the RTL. It should have a Verilog Test Bench with
> non-scan test vectors. The corresponding set can also be provided in a simple
> format like a table.

Dear ladies and gentlemen,

I have some comments and questions on this topic. First, I believe this set
of benchmarks are for checking out test tools, methodology, and algorithms.
Why then do we need the benchmarks in synthesizable rtl? We should not be
checking out efficiencies or the nuances of synthesis. That's a whole
different area.

I believe the minimum requirement is a gate-level description with its
corresponding cell library and with no test structures inserted, scan, bist,
or whatever. In this case the "language" of the design, be it verilog, VHDL,
etc. is of little consequence since they can all be easily converted from
one another. Even if all one can get is a design with scan inserted, it's
fairly simple to remove the scan circuitry. Also with this approach,
no test benches are needed.

So I have pared the minimum requirement down to two items - a gate-level
netlist and a cell library. Even these may be hard to obtain from commercial
suppliers. Can we simplify the equation further :-)

Regards,
Luis

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