Re: Exchange of mail on Test benches and benchmark requirements

[Rainer Dorsch <rainer@rainer.informatik.uni-stuttgart.de>]

> Perhaps everyone submitting a circuit could also submit a form like this:
> 
> 
>            RTL            |  Netlist               |  Library
> --------------------------------------------------------------------------
> Design    VHDL | Verilog  | Verilog | EDIF | VHDL  | Verilog | Bench | Prop.
> 
> 
> With checkmarks if the circuit were available in the particular format.
> As time goes on, we could get more boxes filled in, as we got people to do 
> translations, as Gordon suggests.  I definitely agree that for the first pass we 
> do not need all the boxes checked. 
> 

As a user, I need to read one of the file formats and build a graph-like data 
structures in RAM. From my point of view, it would be much easier to use a 
library which already can read one of these formats and build this data 
structure (except I need a very special structure for my algorithm to work 
efficient).

If such a library would be provided, I guess 80% of the tools would build on 
this data structure and linking two tools together would be much easier. It is 
somewhat offtopic, but if filters are created, this would be only little more 
work and the tools would be much more comparable and _compatible_.

Maybe there is already something like this and I do not know it.


-- 
Rainer Dorsch
Abt. Rechnerarchitektur  e-mail:rainer.dorsch@informatik.uni-stuttgart.de
Uni Stuttgart            Tel.: 0711-7816-215