Re: Exchange of mail on Test benches and benchmark requirements

[Scott Davidson <scottdav@hsmpk12a-s1>]

> From: Franc Brglez <brglez@zodiac.cbl.ncsu.edu>

> 
> I have been short on bandwidth for the last few weeks and apologize if I am
> repeating any of the suggestions below:
> 
> -- it would be useful to have a web-based archival site of all such
> correspondence. An example of how such a site (with a search engine) and
> threaded index may look like, see (and try out) under
>       http://www.cbl.ncsu.edu/DiscussionGroups/A-GuestUser-Test-Forum/
> 
I am setting up a website for the benchmarks, which will include 
a mail archive.  Thanks for the suggestion, I will take a look at
this site.  The site will be hosted by UT Austin, thanks to the good
graces of Jacob Abraham.  However, I expect you have benchmark distribution
facilities better than anyone else.  Could we make use of those?

I'll only be at DAC Monday.  Who would be interested in attending a
meeting at ITC?  I'll set one up - and I think we can get it announced at the 
plenary.

> 
> -- there may be still time to set up a meeting at DAC -- I am away from
> e-mail next week, but Scott may come up with something .... see me at
> Univ-Booth 11-1pm each day, the 6-university team project (as per 1998 June
> IEEE spectrum article gives some hints of things to be seen) -- for foils
> under construction, see
>     http://www.cbl.ncsu.edu/publications_misc/1998--Talk-DACdemo/
> 

<snip>
> 
> 
> Here we see that TWC (total wire crossing) in 100 instances of ISOMORHIC
> circuit c1355, can vary -- when placed by the same tool -- from 2293 to
> 4378!!
> 
> You should expect similar variations in "test length" when you give the
> tool 100 identical netlists and fault lists in different order!!! For more
> details on the "design of experiments", see my draft tutorial report,
> entitled "Design of Experiments to Evaluate CAD Algorithms: Which
> Improvements Are Due to Improved Heuristic and Which Are Merely Due to
> Chance?", accessible under
>       http://www.cbl.ncsu.edu/publications/#1998-TR@CBL-04-Brglez

Actually, some ATPG tools manipulate fault list ordering in order to
reduce test length and run time.  It's one of those tricks that could possibly 
use some rigor.
> 

Scott Davidson
Sun Microsystems
scott.davidson@eng.sun.com