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It is widely recognized that
process variation is emerging as a fundamental challenge to IC design in scaled
CMOS technology; and it will have profound impact on nearly all aspects of
circuit performance. While some of the negative effects of variability can
be handled with improvements in the manufacturing process, the industry is
starting to accept the fact that some of the effects are better mitigated
during the design process. Handling variability in the design process will
require accurate and appropriate models of variability and its dependence
on designable parameters (i.e. layout), and its spatial and temporal
distributions. It also requires carefully designed test structures and
proper statistical data analysis methods to extract meaningful models from
large volumes of silicon measurements. The resulting compact modeling of
systematic, random, spatial, and temporal variations is essential to
abstract the physical level variations into a format the designers (and
more importantly, the tools they use) can utilize. This workshop provides a
forum to discuss current practice as well as near future research needs in
test structure design, variability characterization, compact variability
modeling, and statistical simulation.
Key Topics
Physics mechanisms and technology trends of device-level variations
First-principles simulation methods for predicting variability
Time-dependent variation and their interaction with other variation sources
Compact modeling of variations in devices and interconnect
Device and circuit level modeling techniques
Test structure design for variability
Design interface with manufacturing and solutions for variability
Variability characterization, bounding and extraction
Statistical data analysis and model extraction methods
Novel implementation and simulation techniques for dealing with variability
Tentative Agenda
8:45 9:00am Opening Remarks
Session 1:
Infrastructure for Variability
9:00
9:30am Keynote: Mark Lundstrom (Purdue University)
The NEEDS Initiative: Devices, Circuits, and Systems
9:30 10:00am Muhammad Ashraf Alam (Purdue University)
Too Hot to Handle? The Emerging Challenge of Variability/ Reliability
due to Self-heating in Modern FINFET, ETSOI, and Gate-All-Around
III-V Transistors
10:00 10:30am Tianshi Wang, Aadithya Karthik and Jaijeet Roychowdhury (UC Berkeley)
The Berkeley Model and Algorithm Prototyping Platform
10:30 11:00am
Morning Break/Discussion
Session 2:
Excursions in Variability
11:00 11:30am
Hiroyuki Matsui (University of Tokyo)
Overview of Organic Transistors: From Device Physics to Applications
11:30 12:00am
Swarup Bhunia (University of Florida)
Exploiting Variability in Building Hardware Security Primitives
12:00 12:30pm
Runsheng Wang (Peking University)
Understanding dynamic variability and end-of-life yield in the nanoreliability
era: from devices to circuits
12:30 1:30pm
Lunch
Session 3: Understanding Variability
1:30 2:15pm Afternoon Keynote:
Xin Li (Carnegie Mellon University)
Variability Analysis and Optimization for Analog and Mixed-Signal
Circuits: Challenges and Opportunities
2:15 2:45pm Subhashish Mitra (Stanford University)
Carbon Nanotube Circuits: Imperfections and Variations
2:45 3:15pm
Zheng Zhang (Argonne National Labs) and Luca Daniel (MIT)
State of the Art and Recent Progress in Uncertainty Quantification for
Electronic Systems
3:15 3:45pm Afternoon Break/Discussion
3:45 4:30pm Poster Presentations (5 minutes overview for each poster)
4:30 5:30pm Poster Session
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