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It is widely recognized that
process variation is emerging as a fundamental challenge to IC design in scaled
CMOS technology; and it will have profound impact on nearly all aspects of
circuit performance. While some of the negative effects of variability can
be handled with improvements in the manufacturing process, the industry is
starting to accept the fact that some of the effects are better mitigated
during the design process. Handling variability in the design process will
require accurate and appropriate models of variability and its dependence
on designable parameters (i.e. layout), and its spatial and temporal
distributions. It also requires carefully designed test structures and
proper statistical data analysis methods to extract meaningful models from
large volumes of silicon measurements. The resulting compact modeling of
systematic, random, spatial, and temporal variations is essential to
abstract the physical level variations into a format the designers (and
more importantly, the tools they use) can utilize. This workshop provides a
forum to discuss current practice as well as near future research needs in
test structure design, variability characterization, compact variability
modeling, and statistical simulation.
Key Topics
Physics mechanisms and technology trends of device-level variations
First-principles simulation methods for predicting variability
Time-dependent variation and their interaction with other variation sources
Compact modeling of variations in devices and interconnect
Device and circuit level modeling techniques
Test structure design for variability
Design interface with manufacturing and solutions for variability
Variability characterization, bounding and extraction
Statistical data analysis and model extraction methods
Novel implementation and simulation techniques for dealing with variability
Tentative Agenda
8:45 – 9:00am
Opening Remarks
Session 1:
Beyond Traditional Computing – From Materials to Systems
9:00 – 9:45am
Morning Keynote:
Kaushik Roy (Purdue University)
Brain-Inspired Computing Enabled By Spin Devices: Prospects and Perspectives
9:45 – 10:15am
Lei He (UCLA)
Boolean Satisfiability by Quantum Annealing
10:15 – 10:45am
Zhihong Chen (Purdue University)
Nanomagnet Networks as Building Blocks for Ising Computing
10:45 – 11:00am
Break
Session 2:
Emerging Devices and Reliability
11:00 – 11:30am
Masanori Hashimoto (Osaka University)
Highly-Dense Reconfigurable Architecture with Overlay Via-Switch Crossbar
11:30 – 12:00am
Takashi Tokuda, Toshihiko Noda, Kiyotaka Sasagawa, and Jun Ohta (NAIST)
Design and Evaluation of Implantable CMOS Chips
12:00 – 1:00pm
Lunch
Session 3:
Coping With Lithographical Variability in Advanced Technologies
1:00 – 1:45pm
Afternoon Keynote:
Henry Smith (MIT / LumArray)
Zone-Plate-Array Lithography: A Disruptive Technology
1:45 – 2:15pm
Kafai Lai and Terrence Hook (IBM)
Modeling Directed Self Assembly Patterning and Its Impact on Future Devices' Sensitivity
2:15 – 2:45pm
Haydon Taylor (UC Berkeley)
Defectivity Simulation in Nanoimprint Lithography Using a Boundary Element Model for Resist Droplet Spreading and Coalescence
2:45 – 3:15pm
Afternoon Break/Discussion
3:15 – 4:00pm
Poster Presentations (3 minutes overview for each poster)
4:00 – 5:00pm
Poster Session
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