|
Variability has emerged as a fundamental challenge to IC design in scaled CMOS technology; and it has profound impact on nearly all aspects of circuit performance. While some of the negative effects of variability can be handled via improvements in the manufacturing process, comprehensive methods are necessary to assess and manage the negative effects of variability, which in turn requires accurate and tractable variability models. The goal of the VMC workshop is to provide a forum for theoreticians and practitioners to freely exchange opinions on current practices as well as future research needs in variability modeling and characterization.
The workshop organizers strongly encourage the submission of early results in the related topics. The submissions will be evaluated by the Technical Program Committee, and the author(s) of the accepted submissions are expected to present the results in the format of posters and few-minutes introductory presentations at the workshop. Proceedings of the workshop are limited to the attendees.
Key Topics
Fundamental physics of device variability
Compact variability modeling development and applications
Statistical extraction of variability
Variability test structure design and calibration
Design interface with manufacturing and solutions for variability
Variability issues in emerging semiconductor technology
Temporal variability issues
Reliability considerations that may be closely related to variability
Variability in computing and systems
Agenda
8:45 – 9:00am
Opening Remarks
Session 1:
Frontiers of Computing
9:00 – 9:45am
Morning Keynote:
Fadi Kurdahi (UC Irvine)
Revisiting the Perfect Chip Paradigm: Cross-Layer Approaches to Designing
and Monitoring Reliable Systems using Unreliable Components
9:45 – 10:15am
Vijay Narayanan (Pennsylvania State University)
Is it Logic or Memory? - Blurring the gap
10:15 – 10:45am
Tajana Simunic Rosing (UC San Diego)
Increasing computational efficiency with novel computing paradigms
10:45 – 11:00am
Break
Session 2:
MEMS and Optics
11:00 – 11:30am
Yoshio Mita (University of Tokyo)
Visualizing is Believing - Test Structures for Deep-Etched High
Aspect Ratio MEMS Process and Device Characterization
11:30 – 12:00am
Peter McMahon (Stanford University)
Computing using networks of optical parametric oscillators
12:00 – 1:00pm
Lunch
Session 3:
Memory of the Future
1:00 – 1:45pm
Afternoon Keynote:
Hai Li (Duke University)
Enhance the Reliability and Scalability of
Memristor-based Neuromorphic Systems
1:45 – 2:15pm
Vivek Seshadri (Microsoft)
Processing Using Memory: Mechanisms, Benefits, and Challenges
2:15 – 2:45pm
Haitong Li (Stanford University)
3D Vertical Resistive RAM (VRRAM) for In-Memory Computing
2:45 – 3:00pm
Afternoon Break/Discussion
Session 4:
Conclusionary Talk and Posters
3:00 – 3:30pm
Hidetoshi Onodera (Kyoto University)
Toward Minimum Energy Operation of Voltage-Scaled Circuits
3:30 – 4:00pm
Poster Presentations (time equally divided for each poster)
4:00 – 4:30pm
Poster Session and Networking
|
