Minutes of ITC'99 Benchmark Meeting

Marriott Wardman Hotel, Washington DC

October 20, 1998

Minutes by Scott Davidson - 11/4/98

Scott Davidson Sun Microsystems hyungwon@eecs.umich.edu 734 936-2828
Mark HansenDelphi- Delco Electronicsmchansen@icdc.delco.elect.com765 451-3004
Scott FetherstonAMDscott.fetherston@amd.com408 774-7778
Matteo Sonza ReordaPolitecnico di Torino sonza@polito.it 39 011 564 7055
Dennis Lewis Mitel Semiconductordennis_lewis@mitel.com613 592-2122
Jim ArmstrongVirginia Techjra@vt.edu540 231-4723
Hank FlynnFlynn Systems Corp.hank@flynn.com603-598-4444
Matt Van WagnerFlynn Systems Corp.matt@flynn.com603-598-4444
Rainer DorschUniversity of Stuttgart rainer@rainer.informatik.uni-stuttgart.de49-777-7816-275
Hank WalkerTexas A&M Universitywalker@cs.tamu.edu409 862-4387
Mahesh IyerSynopsysmiyer@synopsys.com
Matthew MichelsLSI Logicmattm@computer.org970 223-5100 x9358



The foils presented by Scott - PostScript or PDF

Formats and Benchmark Requirements

There was considerable discussion on this topic, in several areas.

RTL Format

It was the consensus that both VHDL and Verilog were acceptable, since most or all universities have access to synthesis tools. There was a request for behavioral level examples, however few are known of in industry that might be good benchmark candidates.


Libraries are a major problem. The consensus of the group was that a new, generic library was not acceptable since it would not be realistic. For instance, for some purposes (such as generation of tests for bridging faults) cell drive strengths are required.

The .lib format from Synopsys might be open. (Mahesh said he would check.) This would make a good standard format. It might be possible to get old libraries from IC vendors - the LSI Logic 10k library was mentioned as an example.

Mahesh also said that it might be possible to technology map benchmarks done in another library to the standard, provided library.

Action Item: Mahesh Iyer. Investigate library issues, determine if .lib is open enough, and see if old vendor libraries can be donated.

Benchmark Circuits

There was a long discussion on characteristics of the benchmarks. People wanted to see benchmark circuits at the behavioral level, custom design level, and many things in between. No consensus was reached.

Scott later attempted to address these issues in an email, here referenced. An important point is that benchmark collection and refinement should be a continuing process, so that missing features, additional representations, and extended fault lists can be added in later releases of the benchmarks.

High Level Versions of the ISCAS '85 and '89 Benchmarks (Mark Hansen).

Mark described work at the University of Michigan in understanding the structure of these circuits and providing RTL level versions of some of them. These are useful in testing RTL test generation capability.

The benchmarks are available at their website.

Politecnico di Torino Benchmarks - Matteo Sonza Reorda

Matteo described their benchmark set, which includes both RTL and gate level versions of a range of designs. These are targeted for RTL level test generation and DFT. The benchmarks are available from their website.

These benchmarks are not meant to fully match the functionality of the original circuits. In fact, multiple clock designs have been modified to use one clock.

Links to both these benchmark sets will be provided with the benchmarks, and some might be included in the official set in order to test test generation tools.

Next Steps


This is an update on the status of the benchmark effort.

Please send comments and corrections to Scott Davidson.

Please visit the benchmark website.

Scott Davidson
Last modified: Fri Nov 6 14:49:43 PST