Minutes by Scott Davidson - 11/4/98
|Scott Davidson||Sun Microsystemsemail@example.com||734 936-2828|
|Mark Hansen||Delphi- Delco Electronicsfirstname.lastname@example.org||765 451-3004|
|Scott Fetherston||AMDemail@example.com||408 774-7778|
|Matteo Sonza Reorda||Politecnico di Torinofirstname.lastname@example.org||39 011 564 7055|
|Dennis Lewis||Mitel Semiconductoremail@example.com||613 592-2122|
|Jim Armstrong||Virginia Techfirstname.lastname@example.org||540 231-4723|
|Hank Flynn||Flynn Systems Corp.||email@example.com||603-598-4444|
|Matt Van Wagner||Flynn Systems Corp.||firstname.lastname@example.org||603-598-4444|
|Rainer Dorsch||University of Stuttgartemail@example.com||49-777-7816-275|
|Hank Walker||Texas A&M Universityfirstname.lastname@example.org||409 862-4387|
|Matthew Michels||LSI Logicemail@example.com||970 223-5100 x9358|
There was considerable discussion on this topic, in several areas.
Libraries are a major problem. The consensus of the group was that a new, generic library was not acceptable since it would not be realistic. For instance, for some purposes (such as generation of tests for bridging faults) cell drive strengths are required.
The .lib format from Synopsys might be open. (Mahesh said he would check.) This would make a good standard format. It might be possible to get old libraries from IC vendors - the LSI Logic 10k library was mentioned as an example.
Mahesh also said that it might be possible to technology map benchmarks done in another library to the standard, provided library.
Action Item: Mahesh Iyer. Investigate library issues, determine if .lib is open enough, and see if old vendor libraries can be donated.
There was a long discussion on characteristics of the benchmarks. People wanted to see benchmark circuits at the behavioral level, custom design level, and many things in between. No consensus was reached.
Scott later attempted to address these issues in an email, here referenced. An important point is that benchmark collection and refinement should be a continuing process, so that missing features, additional representations, and extended fault lists can be added in later releases of the benchmarks.
Mark described work at the University of Michigan in understanding the structure of these circuits and providing RTL level versions of some of them. These are useful in testing RTL test generation capability.
The benchmarks are available at their website.
Matteo described their benchmark set, which includes both RTL and gate level versions of a range of designs. These are targeted for RTL level test generation and DFT. The benchmarks are available from their website.
These benchmarks are not meant to fully match the functionality of the original circuits. In fact, multiple clock designs have been modified to use one clock.
Links to both these benchmark sets will be provided with the benchmarks, and some might be included in the official set in order to test test generation tools.
This is an update on the status of the benchmark effort.
Attempts are continuing to get more circuits. However, these three are a good start.
Please send comments and corrections to Scott Davidson.
Please visit the benchmark website.