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It is widely recognized that
process variation is emerging as a fundamental challenge to IC design with
scaled CMOS technology; and that it will have profound impact on nearly all
aspects of circuit performance. While some of the negative effects of
variability can be handled with improvements in the manufacturing process,
the industry is starting to accept the fact that some of the effects are
better mitigated during the design process. Handling variability in the
design process will require accurate and appropriate models of variability
and its dependence on designable parameters (i.e. layout), and its spatial
and temporal distribution. Such models are quite different from the
“corner” models deployed thus far to model manufacturing variability.
As a consequence, the compact modeling of systematic, spatial, and random
variations is essential to abstract the physical level variations into a
format the designers (and –importantly- the tools that they use) can
utilize. This IEEE/ACM workshop provides a forum to discuss current
practice as well as near future research needs in the compact variation
modeling.
Report from CVM
2008: PDF
Key Topics
 Physics mechanisms and
technology trends of device-level variations
First-principles
simulation methods for predicting variability
Compact modeling of
variations in devices and interconnect
Novel implementation and
simulation techniques for dealing with variability
Variability bounding,
characterization and extraction
Device and circuit level
modeling techniques
Speakers and
Tentative Agenda (talk
abstract in PDF)
8:25 – 8:30am
Opening Remarks
8:30 – 9:50am
Session I: The Needs of Variational Compact Models
Luigi Capodieci (AMD): Managed Variability: Present and Future of
Design-Process Integration from 45nm, and 32nm, to 22nm and Beyond
Samar Saha (SilTerra): Variability in Scaled CMOS Technology and Modeling Approaches for Circuit
Simulation
9:50 – 10:20am Morning
Break/Discussion
10:20 – 11:40am Session II: Current
Statistical Device Model
Colin McAndrew (Freescale): Backward
Propagation of Variance: You Measure it, BPV can Model it!
John Krick (TI): Statistical Transistor SPICE Modeling in Advanced CMOS Technologies
11:40 – 1:00pm Lunch
1:00 – 3:00pm
Session III: Practice on Variation Modeling
Chenming Hu (UC Berkeley): Compact Models of Some MOSFET Variations
Joe Watts (IBM): A Multilevel Approach to Statistical Compact Modeling
Xi-Wei Lin (Synopsys): Modeling of Proximity
Effects in Nanometer MOSFET
3:00 – 3:30pm
Afternoon Break/Discussion
3:30 – 4:50pm
Session IV: Statistical Characterization and Simulation
Bruce McGaughy (ProPlus): Model Extraction
and Simulation Challenges for Process Variations in 45nm and Below
Kishore Singhal (Synopsys): Display and
Analysis of Variability Simulation Results
4:50 – 5:10pm
Closing Remarks
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