1. Create new library
2.
Schematic Composer
3. Netlist
generation using Verilog-XL
Next we are going to generate the netlist. The netlist describes the connection between cells. PRIMETIME and APR tools depend on the netlist to recreate the design in timing analysis and place-&-route.
First start the verilog simulator by clicking Tools -> Simulation -> Verilog-XL. Click OK.
Then in Verilog simulation window, click Setup->Netlist... click more in the pop up window. Enter choice as the following:
Click OK. Then click Simulation ->Start Interactive, after a while, click Simulation -> Continue
Make sure there is no error in the log window.
When simulation is done, you can check the netlisting result in File->View Netlist Result->verilog.inpfiles. It is like the following window:
Then close the window and close icfb.