The research emphasis in this area is to develop new techniques for generating high quality tests for very large designs. We believe that the complexity of test generation can be managed only by a hierarchical approach which exploits information about the behavior of the design (included in the behavioral and RTL simulation models developed early in the design cycle). Techniques are being developed to extract useful test information automatically from the high level simulation models and to use this information to develop thorough tests. In cases where the fault coverage is not adequate or where the test length is excessive, modifications are suggested to the behavioral models to improve the testability of the design. Results from formal verification are used to achieve these goals. Target systems include complex processors and ASICs as well as analog and mixed-signal systems.
Research projects include:
Use of
Genetic algorithms to generate tests for large sequential
circuits Automatic
extraction of test knowledge from behavioral modelsxm Behavioral
modifications for testability Self-test
techniques for complex processors Timing
verification and test generation for delay and crosstalk faults Fault
modeling and test generation for analog and mixed-signal circuits Integrated
approaches to test and verification
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