1. Introduction
2. Setting up
the environment
3. Starting Cadence
4. Library Manager
5. Creating new library
6. Creating new cell
7. Schematic Composer
8. Creating Symbols
9. Logic Simulation with
Verilog-XL
10. Custom layout with
Virtuoso
11. Layout Extraction
12. Layout Vs. Schematic (LVS)
13. Abstract view
In this major section, we will use Cadence Design Environment to create several views for a standard cell. These views include schematic view, symbol view, layout view, extracted view, and abstract view which gives the functional, behavioral, and physical information about the cell.
In the following instructions, we will discover how to use Custom IC design tools to created these views. The tools we are going to use include:
Virtuoso Schematic Composer
Virtuoso Symbol Editor
Virtuoso Layout Editor
Verilog-XL simulation
DIVA - DRC, extraction, abstract and LVS verification tools