1. Introduction
2. Setting up
the environment
3. Starting Cadence
4. Library Manager
5. Creating new library
6. Creating new cell
7. Schematic Composer
8. Creating Symbols
9. Logic Simulation with
Verilog-XL
10. Custom layout with
Virtuoso
11. Layout Extraction
12. Layout Vs. Schematic (LVS)
13. Abstract view
Now we are going to create a new cell library.
In Library Manager window, click File -> New -> Library...
A new window labeled "Create Library" will appear:
In the Name field, type in the standard cell library name: SimpleSCL
In the Technology Library field, choose Attach to existing tech library. Then choose TSMC 0.20u CMOS018(6M, HV FET, sblock)
Click OK
We can see SimpleSCL is added in the Library column in Library Manager window.